The invention relates to the technical field of
chip scheduling and optimization, in particular to a neural network-based main control
chip task scheduling and dynamic performance optimization method, which comprises the steps of
data acquisition and
feature engineering, neural
network model design,
simulation environment training,
model compression and deployment preparation, real-time state monitoring, dynamic decision reasoning, scheduling
strategy execution and performance optimization. The
data acquisition and
feature engineering comprises the following steps: S1, hardware index acquisition; analyzing task attributes (calculation-intensive / IO-intensive), a dependency relationship (DAG), deadline (Deadline) and a resource demand (CPU / GPU
occupancy rate); collecting data during
chip operation through a performance counter (IPC,
cache hit rate and
branch prediction error rate), a temperature sensor and a
power consumption monitoring unit (PMU); the neural
network scheduler can achieve the energy efficiency ratio which is 20%-40% higher than that of a traditional method (such as a CFS scheduler), meanwhile, the neural
network scheduler adapts to sudden load changes, and the practicability and the application range of a main control chip are wider.