40 results about "Primary status" patented technology

From among a plurality of threads accessing a shared data object, one thread acquires a “master” status to arbitrate among the requests of competing threads during a given session of data access to the shared data object. During the session, the master thread resolves any conflicts resulting from attempts to access or modify the shared data object by other threads, and only the master thread may apply modifications to the shared data object during the session. Meanwhile, during the session, non-master threads may perform non-blocking read operations on the shared data object. During a subsequent session, a different thread may acquire master status.

A computer-implemented method for distributing a plurality of data partitions among a cluster of computer nodes includes dividing a database into a plurality of primary partitions, storing the primary partitions on a plurality of nodes associated with a computer network, duplicating the primary partitions to create a plurality of secondary partitions and storing the secondary partitions on the nodes, wherein the primary and secondary partitions are substantially evenly distributed among the nodes, each secondary partition is stored on a different node than its corresponding primary partition, diversity exists with respect to each secondary partition and the node where it is stored, the primary partitions are available to serve a system workload, and one or more secondary partitions corresponding to one or more primary partitions of a failed node are available to be upgraded to primary status to maintain workload balancing and data availability after one of the computer nodes fails.

One embodiment includes a future activity list (FAL) maintained within a peripheral bus host controller. The FAL includes information indicating for a number of peripheral bus frames whether those frames will have activity or are null. For frames that will have activity, the host controller performs a system memory read to gather information required to process the active frame. For frames that are null, the host controller does not perform the system memory read. A bus master status bit is pegged (continually set to “true”) by the host controller only when the host controller is processing an active frame. Because the bus master status bit is not pegged by the host controller during null frames, there is greater opportunity for an operating system to enter lower power states.

An information handling system is provided. The information handling system includes at least one server, that includes a plurality of ports, wherein information is transmitted to and from the at least one server on the plurality of ports, and a memory storing a table, the table storing a status indication and port on which the status indication was received. The information handling system also includes a plurality of switches coupled to the at least one server to form a link aggregation group (LAG), the plurality of switches transmitting information including the status indication to the at least one server. If the server receives more than one status indication having a master status, the at least one server is configured to stop forwarding information on at least one port on which information including a master status indication has been received after previously receiving information that did not include a master status indication.

A method for fault tolerant controller readiness. Executing functions by a first controller operating in a primary status mode. Operating in a hot standby status mode by a second controller and mirroring the first controller by executing functions to operate as a redundant controller. Operating in a cold standby status mode by at least one backup controller under normal operating conditions. The second controller is reconfigured while operating under normal operating conditions from the hot standby status mode to the primary standby status mode if a failure occurs in the first controller. Reconfiguring the at least one backup controller operating under normal operating conditions from cold standby status mode to hot standby status mode to operate as a redundant controller in response to the reconfiguring the second controller from the hot standby status mode to the primary status mode.

The invention discloses an Ethernet communication master station implementation method, comprising an Ethernet, a master station and a slave station, wherein the master station is connected with the Ethernet by a connector, and forms a bus structure with the slave station which is connected with the master station by the Ethernet; the method specifically comprises the following steps: a initializing the master station and scanning the bus, b configuring the bus and synchronously monitoring the real-time state of the bus, and c entering to the normal running stage by the bus so as to finish data communication work between the master station and the slave station. The method has beneficial effects that the master station can dynamically adjust the instruction sending time according to system task scheduling jitter and application program execution time jitter, so as to ensure the consistency of the rhythms of the master station and the slave station in reading and writing data, the real-time requirement of the method to the master station is not very high, and the allowed system task scheduling jitter is larger and larger along with the shortening of the execution time of the upper application program.

A multi-core processor system, a dynamic power management method thereof and a control apparatus thereof are provided. In the method, a workload of a multi-core processor during a runtime stage is obtained. Next, a hot-plug operation is respectively performed on a plurality of slave cores according to the workload and a working state of each slave core. Then, a bus master status and the working state of a boot core are monitored to determine whether to power off the boot core, in which the bus master status is generated by combining a plurality of device statuses reflected by a plurality of peripheral devices. Finally, when the bus master status is determined as idle, the boot core is powered off.