Selective emitter structure, its preparation method and application
An emitter and selective technology, applied in photovoltaic power generation, climate sustainability, final product manufacturing, etc., can solve the problem of battery open circuit voltage and fill factor, metal diffusion into the interior of monocrystalline silicon, equipment and pipeline life effects, etc. problem, achieve the effect of reducing carrier recombination, excellent passivation effect, and avoiding the existence of high recombination area
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preparation example Construction
[0062] In some embodiments, the preparation method further includes: forming the first dielectric layer on the surface of the silicon substrate by at least any one of oxidation, physical or chemical deposition, but not limited thereto. The oxidation method includes but not limited to wet chemical oxidation method, high temperature oxidation method, plasma assisted oxidation method, ozone oxidation method or other surface oxidation methods and the like. The physical or chemical deposition methods include, but are not limited to, plasma-assisted atomic layer deposition, plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), and the like.
[0063] In some embodiments, the preparation method further includes: at least a chemical vapor deposition method or a physical vapor deposition method combined with an in-situ doping method or a secondary doping method can be selected to form a preparation method on the first dielectric layer. A heav...
Embodiment 1
[0087] Embodiment 1 The preparation method of a selective emitter structure provided in this embodiment includes the following steps:
[0088] (1) Cleaning and double-sided alkali polishing of n-type silicon wafers;
[0089] (2) Using PECVD in-situ oxidation method to prepare ultra-thin silicon oxide layers (thickness greater than 0 and less than 3nm) on both the front and back sides of the silicon wafer;
[0090] (3) Prepare a boron-doped amorphous silicon oxide film with a thickness of 60-300 nm on the front and back sides of the silicon wafer by PECVD method (wherein the boron atomic concentration is 1E17 cm -3 ~5E20cm -3 , the oxygen atomic concentration is 0.1at%~50at%, and the oxygen content on the side near the surface of the silicon wafer is low, and the oxygen content on the side away from the surface of the silicon wafer is high), and then at 900°C to 1000°C with multiple different annealing times ( 1min~600min) for high temperature annealing to form a boron-doped ...
Embodiment 2
[0103] Embodiment 2 refers to Figure 4 As shown, the n-TOPCon crystalline silicon cell based on an n-type silicon chip provided by this embodiment includes an n-type silicon chip, the front side of the n-type silicon chip is covered with a p-type boron-doped emitter, and the boron-doped emitter Several selective emitter structures are distributed on the electrode, wherein the selective emitter structure includes an ultra-thin silicon oxide layer and a boron-doped polysilicon oxide layer stacked in sequence, and the boron-doped polysilicon oxide layer is combined with a metal electrode (defined as the first An electrode), and the selective emitter structure and the boron-doped emitter are also covered with an aluminum oxide layer and a silicon nitride layer in sequence, and the first electrode is exposed from the aluminum oxide layer and the silicon nitride layer. A diffusion doped layer is formed on the back side of the n-type silicon wafer, and an ultra-thin silicon oxide la...
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