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4 results about "Packed pixel" patented technology

In packed pixel or chunky framebuffer organization, the bits defining each pixel are clustered and stored consecutively. For example, if there are 16 bits per pixel, each pixel is represented in two consecutive (contiguous) 8-bit bytes in the framebuffer (a.k.a. screen buffer). If there are 4 bits per pixel, each frame buffer byte defines two pixels, one in each nibble. The latter example is as opposed to storing a single 4-bit pixel in a byte, leaving 4 bits of the byte unused. If a pixel has more than one channel, the channels are interleaved when using packed pixel organization. This is as opposed to planar organization, where each channel is stored in its own plane.

Method for managing image data, and vehicle lighting system

The invention relates to a method for managing image data in an motor vehicle lighting system, the lighting system including at least one lighting module intended to project light beams generated on the basis of data relating to the selection of at least one image. The method including receiving an instruction to activate at least one image to be projected, converting the original image into N grey levels, determining, for each pixel in each row in the matrix, whether the pixel under analysis is a significant point of inflection, storing the pixel under analysis as a compressed pixel in a list when the pixel under analysis is considered to be a significant point of inflection, and transmitting the list to the at least one lighting module so that it is able to project a resulting image.
Owner:VALEO VISION SA

A pixel block arrangement method and system for gigapixel

This invention discloses a pixel block arrangement method and system for billion-pixel images. The method includes: inputting the billion-pixel image to be labeled into an inference model and constructing a pixel block tree using initial pixel blocks; performing pixel block filtering based on a pixel block filtering model and the pixel block tree to arrange adjacent fine-grained pixel blocks into corresponding coarse-grained pixel blocks; obtaining a preset number of canvases based on the remaining fine-grained pixel blocks, the corresponding coarse-grained pixel blocks, and a pixel block packing model, and generating final layout information of the packed pixel blocks in the preset number of canvases; optimizing the model based on the final layout information of the packed pixel blocks to obtain a trained inference model; and outputting the labeled data of the billion-pixel image to be labeled and the labels of the labeled data based on the trained inference model. The pixel block arrangement framework proposed in this invention significantly improves the inference speed for billion-pixel images while maintaining ideal performance.
Owner:TSINGHUA UNIVERSITY +1

Display panel and display device

The application provides a display panel and a display device. The display panel comprises a substrate, a driving circuit layer, a pixel definition layer and a plurality of light emitting devices. The display panel provided by the application has a first shortest distance between the orthographic projection of the first via hole on the substrate and the orthographic projection of the corresponding first pixel opening on the substrate, and a second shortest distance between the orthographic projection of the second via hole on the substrate and the orthographic projection of the corresponding second pixel opening on the substrate. The first shortest distance and the second shortest distance are not equal, which is beneficial to compressing the space outside the pixel opening, thereby improving the pixel opening rate, the brightness of the display panel and the display performance of the display panel.
Owner:HEFEI VISIONOX TECH CO LTD +1

Display panel and display device

This application provides a display panel and a display device. The display panel includes a substrate, a driving circuit layer, a pixel defining layer, and multiple light-emitting devices. The driving circuit layer is provided with multiple pixel driving units and multiple vias. The multiple pixel driving units include multiple first pixel driving units and multiple second pixel driving units. The multiple vias include multiple first vias and multiple second vias. The pixel defining layer defines multiple first pixel openings and multiple second pixel openings. In the display panel provided by this application, the orthographic projections of the first and second vias on the substrate are located between the orthographic projections of the corresponding first and second pixel openings on the substrate. This facilitates the compression of the space outside the pixel openings, thereby increasing the pixel aperture ratio, improving the brightness of the display panel, and enhancing the display performance of the display panel.
Owner:HEFEI VISIONOX TECH CO LTD +1