3results about How to "Reduce decoding overhead" patented technology

The present invention provides a reliable transmission method for underwater acoustic network data based on online fountain codes. The dynamic parity sequence coding method proposed in the establishment stage realizes the expansion of basic components through rule coding, reduces the number of interconnected components, and thus reduces the number of coding packets and the number of feedbacks required in the completion stage. In the completion stage, the sending of invalid coding packets is avoided as much as possible, and the receiving party's interconnected components are determined by updating the receiving party's decoding diagram, and representative data packets are screened from each component and fed back to the sender. The present invention effectively reduces the number of invalid coding packets sent in the completion stage, thereby reducing the decoding overhead in the completion stage; it also reduces the feedback overhead of the online fountain code, and can realize reliable transmission of data packets with low overhead in underwater acoustic networks with limited bandwidth and energy consumption, reducing the overall decoding overhead, improving the efficiency of data packet transmission in the underwater acoustic network, improving the decoding efficiency, and reducing the overall overhead.

The application belongs to the technical field of solid-state storage, and specifically discloses a solid-state disk fault-aware reading optimization and code length self-adaption method and device, which comprises the following steps: a fault-aware re-reading mechanism is constructed, a code word that fails to be decoded in a primary decoding round is marked, and only the marked failed code word is transmitted in a subsequent re-reading round; based on the fault-aware re-reading mechanism, the delay of hard-decision decoding and the delay of soft-decision decoding are analyzed and combined to obtain a fault-aware reading delay model; the fault-aware reading delay model comprises a default reading operation delay model and a soft-decision reading operation delay model; when reading data, a reading mode determination result is obtained based on the fault-aware reading delay model; when writing data, a target code length in the case of the shortest reading delay is obtained based on the fault-aware reading delay model; and the target code length is used to write data. Through the application, the reading performance of an SSD can be improved under the condition that the code rate remains unchanged.

The invention discloses a dynamic error correction method suitable for a three-dimensional NAND flash memory, a controller and a storage system, and belongs to the technical field of semiconductor storage, and the method comprises the following steps: a coding stage: carrying out polar code coding on data to be written into the three-dimensional NAND flash memory to obtain a code word sequence with the length of N; in the decoding stage, the LLR value of each bit is calculated for the data with the length of N read from the three-dimensional NAND flash memory; after setting the list length of the SCL decoding algorithm, inputting the N-bit LLR value into the SCL decoding algorithm to realize decoding; the step of setting the list length of the SCL decoding algorithm comprises the following steps: acquiring bit error rates of the SCL decoding algorithm under different list lengths under the current original bit error rate of the three-dimensional NAND flash memory, screening the list length with the bit error rate lower than a preset performance threshold, and setting the list length of the SCL decoding algorithm as the screened minimum length. The method adapts to the error characteristic of the three-dimensional NAND flash memory, and the overhead can be reduced under the condition of ensuring that the error correction requirement is met.