A channel estimator (150) is provided that comprises: an extension circuit (410) configured to receive a pilot signal (510), and add front and back extension signals (620, 630) to a front and back of the pilot signal, respectively, creating a first signal (610), the front and back extension signals being extension of a first and last symbol, respectively, in the pilot signal; an IDFT circuit (420) configured to perform an IDFT function on the first signal, generating a second signal (710); a signal processing element (430, 440, 470, 480) configured to perform one or more operations on the second signal, generating a third signal (910); a DFT circuit (450) configured to perform a DFT function on the third signal, generating a fourth signal (1010); and a reduction circuit configured to cut off front and back ends of the fourth signal, generating a channel estimation signal (1110).