39 results about "Cell interconnection" patented technology

The invention discloses a perceptually optimized wiring time sequence prediction method for a digital integrated circuit, electronic equipment and a storage medium, and the method comprises the steps: constructing a heterogeneous graph according to a circuit netlist, fusing the heterogeneous graph with feature vectors corresponding to all units and interconnection lines, inputting the fused heterogeneous graph into a trained heterogeneous graph neural network, and obtaining graph network embedding; inputting the feature matrix of the layout into the trained convolutional neural network to obtain convolutional network embedding; splicing graph network embedding and convolutional network embedding to obtain multi-modal local embedding; constructing a feature sequence of the path according to a connection relationship between a logic unit and an interconnection line in the path by multi-modal local embedding, and inputting the feature sequence of the path into the trained Transform network to obtain a path delay residual prediction value after wiring; and adding the path delay value after layout and the path delay residual prediction value after wiring, and finally obtaining a path delay prediction value after wiring. According to the method, the path delay after wiring can be accurately and efficiently predicted before wiring.

The invention provides an image sensor and a preparation method thereof, and electronic equipment, and the image sensor comprises a semiconductor substrate which comprises a plurality of pixel units which are arranged in an array; the interconnection layer is located on the semiconductor substrate; the storage element layer is located on the semiconductor substrate and comprises a plurality of storage units arranged in an array mode, and the storage units correspond to the pixel units; wherein the storage unit comprises a first polar plate structure and a second polar plate structure, the first polar plate structure comprises an accommodating area, and the second polar plate structure is electrically led out through the accommodating area based on an interconnection layer. According to the invention, the storage element layer is arranged in the interconnection layer, and the storage unit corresponds to the pixel unit, so that the arrangement of the storage element can be effectively realized, the compactness of the device layout can be improved, the lead-out mode of another polar plate structure is realized through the interconnection layer based on the design of the accommodating area, and the process design and the implementation mode can be further optimized.

An apparatus includes an interconnect assembly configured to receive and retain multiple batteries. The interconnect assembly includes a retainer configured to receive portions of the batteries and a conductive interconnect layer carried by the retainer. The conductive interconnect layer includes a first layer of conductive material having a first thickness and a second layer of conductive material having a second thickness less than the first thickness. The first and second layers of conductive material are attached together to form the conductive interconnect layer. The second layer of conductive material includes multiple interconnects configured to be coupled to cathodes and anodes of the batteries.

A memory device and a method of manufacturing the same are provided. The memory device includes a semiconductor substrate, an interconnect structure and a memory cell. The interconnect structure is disposed over the semiconductor substrate, and the memory cell is disposed over the interconnect structure and electrically coupled with the semiconductor substrate and the interconnect structure. The memory cell includes a spin Hall electrode layer, an MTJ pillar, a hard mask, and a spacer. The MTJ pillar is disposed on the spin Hall electrode layer, the hard mask is disposed on the MTJ pillar, and the spacer is disposed on sidewalls of the MTJ pillar and the hard mask. Suitably, the spin Hall electrode layer at least comprises an inner portion and an outer portion surrounding the inner portion, and a top surface of the outer portion is lower than a top surface of the inner portion.

Photovoltaic (PV) cells that can be interconnected with improved interconnect joints to form PV cell strings and PV modules. The improved interconnect joints comprise at least two types of adhesive bonding regions to maximize both electrical conductivity and mechanical strength of interconnect joints coupling terminals of PV cells. The disclosed approaches to PV cell interconnection provide greater manufacturing rates and higher quality PV cell strings and PV modules.

This application discloses a delay prediction method, apparatus, device, and storage medium. The delay prediction method includes: acquiring the unit characteristic information of each unit in a circuit and the characteristic sequence of each unit's interconnection; calculating the equivalent capacitance value of the interconnection path between units based on the capacitance and resistance values ​​of each unit's interconnection, and determining the target interconnection delay characteristics between units based on the equivalent capacitance values; determining the unit delay characteristics of each unit based on the equivalent capacitance values ​​and unit characteristic information; inputting the interconnection delay characteristics and unit delay characteristics into a preset delay prediction model; and performing prediction processing on the interconnection delay characteristics and unit delay characteristics based on the delay prediction model to obtain the delay result of the circuit. This application equates the capacitance and resistance values ​​of each unit's interconnection to equivalent capacitance values, overcoming the deficiency in related technologies where the load capacitance ignores the resistance shielding effect, thereby reducing the error of the load capacitance and improving the accuracy of timing prediction.

The invention provides a back contact photovoltaic cell electrode structure, a photovoltaic cell interconnection method and a cell assembly, the back contact photovoltaic cell electrode structure comprises a first polarity Pad point array, a second polarity Pad point array, a first surface insulation Pad point and a second surface insulation Pad point, the first polarity Pad point array and the second polarity Pad point array are respectively provided with corresponding welding strips along the Pad point extension direction, the welding strip is electrically connected with the Pad point; the first surface insulation Pad point is a surface insulation Pad point at a preset position along the Pad point extension direction of the first polarity Pad point array; and the second surface insulation Pad point is a surface insulation Pad point at a preset position along the Pad point extension direction of the second polarity Pad point array. By arranging the surface insulation Pad points and the welding strips, the invalid occupied space is reduced, the proportion of the effective power generation area in the back contact photovoltaic cell assembly is increased, and then the power generation efficiency is improved.

A system with a switching device is presented. The switching device includes first ports which interconnect first processing units in a first group using a first protocol and includes second ports which interconnect the first processing units with second processing units amongst second groups using the first protocol in conjunction with a second protocol. The switching device includes a switching fabric which determines a destination of an incoming data unit. If the destination is determined to be a first processing unit in the first group, the switching fabric forwards the data unit to a first port of the first ports using the first protocol. If the destination is determined to be a second processing unit in a second group of the second groups, the switching fabric forwards the data unit to a second port of the second ports using the first protocol in conjunction with the second protocol.

This invention discloses an adaptive dual-mode direction backtracking system based on double frequency conversion, comprising a radio frequency (RF) circuit, a control circuit, a local oscillator (LOO), and an antenna array. The RF circuit amplifies, filters, and mixes the RF signals received by the antenna array to form signal transmission links in mixed-mode and Van Atta array modes. The control circuit provides unified control over the RF switches and the transmit / receive delays of each channel, and outputs control signals according to the operating mode switching requirements. The LEO generates and distributes a fixed LEO signal and an adaptive LEO signal to achieve frequency matching under different incoming wave frequencies. The antenna array receives external incoming wave signals and transmits direction backtracking signals, employing an adjacent transceiver unit interconnection method in mixed-mode and a centrally symmetrical array element interconnection method in Van Atta array mode. This invention enables stable direction backtracking under different incoming wave frequencies and different application scenarios.

The invention relates to a wiring parameter determination method and device for a large-size substrate and computer equipment. The method comprises the following steps: acquiring a simulation wiring model of a large-size substrate and process technical data of the large-size interconnection substrate, and identifying each abnormal wiring area in the large-size interconnection substrate; obtaining an optimized wiring parameter of each abnormal wiring area based on the wiring parameter of each unit interconnection line; on the basis of the optimized wiring parameters of all the abnormal wiring areas, integrity index abnormal information of the large-size interconnection substrate is recognized through a connection line splicing integrity evaluation strategy, and new optimized wiring parameters of all the abnormal wiring areas are obtained through adjustment on the basis of the integrity index abnormal information of the large-size interconnection substrate; and iterating until all the integrity index abnormal information meets the preset signal integrity design requirement information, and extracting target wiring parameters of the large-size substrate. By adopting the method, the wiring efficiency of the large-size substrate can be improved.

Embodiments described herein also relate to co-packaged optical and electrical device. The co-packaged optical and electrical device include a package substrate, an electrical or opto-electrical chip disposed on the package substrate, a photonic integrated interconnect unit disposed on the package substrate, a plurality of interconnects, and a plurality of optical structures. The photonic integrated interconnect unit includes a photonic integrated circuit (PIC) including a PIC waveguide. The plurality of interconnects connect the electrical or opto-electrical chip to the photonic integrated interconnect unit. The interconnects are formed on or in the package substrate. The plurality of optical structures are configured to connect the photonic integrated interconnect unit to a fiber optic cable. The plurality of optical structures include a substrate waveguide formed on or in the package substrate. The substrate waveguide is coupled to the PIC waveguide via evanescent coupling.

The addressing of I / O-Modules (I / O) of a Building Automation System shall be simplified. Therefore, there is provided a method of automatically addressing a plurality of I / O-Modules (I / O) of an I / O-Module arrangement being connected to a controller (BAC), the I / O-Modules (I / O) being arranged serially in a first I / O-Bus segment (1) and at least a separate second I / O- Bus segment, each I / O-Bus segment (1, 2) including a branch connection unit (BCC, BCN) and at least one of the I / O-Modules (I / O), the branch connection units(BCC, BCN) of the first and second I / O-Bus segments (1, 2) are interconnected, the method includes the steps of providing pregiven topology data (engineered data) of the I / O-Module arrangement, the pregiven topology data includes for each I / O-Bus segment: a segment address and respective segment topology data, wherein the segment topology data includes an address of the controller or the respective branch connection unit and each I / O-Module (I / O) of the respective I / O-Bus segment, automatically discovering physical segment topology data (fingerprint) by the controller (BAC) in the first I / O-Bus segment (1) and by the respective branch connection module (BCC) in the second I / O-Bus segment (2) and automatically addressing all I / O-Modules with the respective segment address in accordance with the pregiven topology data, only if the physical segment topology data of each I / O-Bus segment (1, 2) corresponds to the respective segment topology data of the pregiven topology data.

The application belongs to the technical field of satellite solar cell assembly, and provides a cell interconnection sheet forming device, which comprises an upper die, a lower die and a supporting assembly. The application designs a special cell interconnection sheet stamping device for the cell of a solar cell array, and designs a special groove module and a convex groove module to finely stamp the interconnection sheet. Considering the accurate positioning of the cell, the application designs a cell positioning rod to accurately position the cell. However, the interconnection sheet has a stretching force during forming. In order to avoid the stress on the root of the interconnection sheet, the application designs a top rod. During forming, the top rod is pressed downward, the positioning rod is moved downward, the movement of the cell is released, the interconnection sheet is accurately formed, and deformation is avoided. When the forming is completed, the positioning rod is lifted, the edge of the cell is lifted, the mold is separated, and the cell is smoothly removed. The whole process achieves the purposes of accurate positioning, accurate forming and convenient operation.

A portable solar photovoltaic (PV) electricity generator module comprises a plurality of smart power slat (SPS) units, each SPS unit comprising a plurality of solar cells electrically connected together based on a specified cell interconnection design, and, at least one power maximizing integrated circuit collecting electricity generated by the plurality of solar cells. The plurality of SPS units are mechanically connected such that the SPS units can be retracted for volume compaction of the module, and can be expanded for increasing PV electricity generation by the module. The module can be used as part of an electric power supply with a maximum power point tracking (MPPT) power optimizer, storage battery and leads to connect to a load. The load can be AC or DC.

A memory device and a method of manufacturing the same are provided. The memory device includes a substrate, a memory cell array, and a memory cell interconnection structure. The memory cell array is disposed on the substrate. Each memory cell in the memory cell array includes a transistor unit and a memory unit that are electrically connected to each other. The memory cell interconnection structure is configured to establish an electrical connection between the memory cells, and includes a dielectric layer and a plurality of drain conductive structures. At least one drain conductive pillar includes a first contact portion and a second contact portion that are connected to each other and embedded in the dielectric layer. One side surface of the first contact portion is recessed along a first direction with respect to one side surface of the second contact portion, so as to form a stepped structure.

The invention discloses a photovoltaic cell interconnection method and a photovoltaic cell assembly, and relates to the technical field of photovoltaic cells, and the method comprises the steps: arranging a positive electrode bus bar at the edge of a first side edge of a plane where a positive electrode of a photovoltaic cell is located, and arranging a negative electrode bus bar at the edge of a second side edge of a plane where a negative electrode of the photovoltaic cell is located, respectively connecting the anode bus bar and the cathode bus bar with an anode welding strip and a cathode welding strip on the photovoltaic cell; the method comprises the following steps of: connecting positive and negative electrode welding strips of a plurality of adjacent photovoltaic cells to form a photovoltaic cell string A, rotating by 180 degrees to obtain a photovoltaic cell string A ', and connecting in series to form a cell string interconnection unit B; mirroring by taking a straight line where the positive and negative output ports of the battery string interconnection unit B are located as an axis to obtain a battery string interconnection unit B ', and connecting in parallel to form a parallel structure; and carrying out transverse expansion on the parallel structure, carrying out series connection to form a series-parallel structure, and packaging each structure to obtain the photovoltaic cell module. According to the invention, the power generation efficiency and matching performance of the photovoltaic cell can be improved.

The application discloses an automatic double-pulse test system and a test method, which comprise an upper computer unit, a controller unit, a capacitor charging and discharging circuit unit, a load inductor unit, an IGBT power unit and an oscilloscope unit; the upper computer unit is interconnected with the controller unit; the controller unit is interconnected with the IGBT power unit; the control end of the controller unit is connected with the input end of the capacitor charging and discharging circuit unit and the load inductor unit; and the output end of the load inductor unit, the capacitor charging and discharging circuit unit and the oscilloscope unit is connected with the IGBT power unit. The whole operation process can be realized through the upper computer. The controller realizes full-automatic control and electrical isolation of the whole double-pulse test circuit, effectively guarantees test safety, the turn-on and turn-off resistance of the IGBT drive can be adjusted on line, operation is convenient, and test efficiency is greatly improved. The automatic double-pulse test system can meet most IGBT double-pulse test scenes, and can directly test the IGBT power module and the capacitor module by quickly connecting the modules with the system.

A communication device includes a sheet structure. The sheet structure includes a plurality of metal units and a plurality of interconnection units. The interconnection units are coupled to the metal units, and are interleaved with the metal units. The interconnection units are controlled according to a plurality of control signals. In response to a first incident wave, the sheet structure can generate a first reflection wave and a first transmission wave.

A data center electrical energy distribution system includes multiple AC, MV DC, and LV DC bus sections. A primary AC source connects to at least one AC bus section, while a secondary AC source connects to either an AC bus section or an MV DC bus section. Each MV DC bus section is linked to a DC source. The AC and LV DC bus sections operate as isolated islands, only connecting through MV DC bus sections. MV DC bus sections form a ring bus, interconnected via semiconductor switching units, which remain closed during normal operation.

The disclosed 3D IC includes a plurality of vertically stacked device tiers, each device tier comprising an SRAM circuit, each SRAM circuit comprising an SRAM bit cell, wherein the bit cells are stacked on top of each other to define a stack of bit cells and wherein and each bit cell comprises first and second pass transistors, first pull-up and pull-down transistors, and second pull-up and pull-down transistors. The SRAM circuits have an identical layout and each SRAM circuit comprises: a single active layer forming an active semiconductor pattern of the transistors of the bit cell, and a single routing layer of horizontally routed conductive lines comprising a complementary pair of first and second bit lines connected to the bit cell of the SRAM circuit, gate lines defining gates of the transistors of the bit cell of the SRAM circuit, and wiring lines forming interconnections of the bit cell of the SRAM circuit.

A semiconductor device includes a first peripheral circuit structure, a second peripheral circuit structure, a first through-via, and a cell structure. The first peripheral structure includes a first substrate that includes a first page buffer region, a first peripheral circuit having a first gate stack having a first height, and first peripheral interconnections. The second peripheral circuit structure includes a second substrate that includes a second page buffer region, a second peripheral circuit having a second gate stack having a second height greater than the first height, second peripheral interconnections. The cell structure includes gate electrodes, channel structures that extend into the gate electrodes, and cell interconnections electrically connected to the gate electrodes and the channel structures.

The invention relates to a laser welding interconnection device (100) for photovoltaic cells (4) to form at least one string of photovoltaic cells (4) interconnected by connecting conductors (6), characterized in that it comprises: a deposit zone (ZD) for at least one photovoltaic cell (4) including a through-hole (O) configured to expose the front and rear faces of said at least one photovoltaic cell (4); a first laser welding unit (20) including a first laser head (20t) configured to perform at least one laser pulse on the front face; and a second laser welding unit including a second laser head configured to perform at least one laser pulse on the rear face, the first (20) and second laser welding units being located on either side of the through-hole (O). Figure 1

The application discloses a crystalline silicon cell, a photovoltaic module and a photovoltaic power generation system, and belongs to the field of ground crystalline silicon solar modules. In view of the problem that, in the prior art, local current enrichment is caused by local connection failure of cell interconnection, local high temperature is generated, the power of the module is reduced, the power generation capacity is reduced, the module is seriously burned to cause a fire, and the consequences are very serious, the application provides a crystalline silicon cell, a photovoltaic module and a photovoltaic power generation system. The crystalline silicon cell comprises silver grid lines, a substrate, a doped region and a back field, the silver grid lines on the upper layer of the doped region are divided into a plurality of regions, and the design of the grid line division reduces current enrichment on the non-failed conductive interconnection material when part of the conductive interconnection material fails. The application reduces the problem of local current enrichment caused by local connection failure of cell interconnection in the crystalline silicon photovoltaic module, and improves the safety of the photovoltaic power generation system.

The invention relates to a laser welding interconnection device (100) of photovoltaic cells (4) to form at least one chain (S) of photovoltaic cells (4) interconnected by connecting conductors (6), characterized in that it comprises: a laser welding unit (20) comprising a laser head (20t) configured to perform at least one laser shot for the local fusion of at least one connecting conductor (6) positioned on the front face (4a) or the rear face (4b) of at least one photovoltaic cell (4); and a turning unit (30), comprising a first gripping member (30p1) for gripping one of the front face (4a) or the rear face (4b), capable of pivoting through a first angle of rotation (R1) of at least 180°, and a second gripping member (30p2) for gripping the other of the front face (4a) or the rear face (4b). Figure for the abbreviation: Figure 1

The invention belongs to the photovoltaic field, and particularly relates to a battery interconnection structure, a photovoltaic module and a preparation method. The battery interconnection structure comprises a battery piece, a bonding strip and a welding strip, the cell piece comprises a perovskite top cell and a crystalline silicon bottom cell, the cell piece is divided into an active area and an inactive area along the width direction of the cell piece, and the active area is an area corresponding to the perovskite top cell covering the crystalline silicon bottom cell; the inactive region is a region corresponding to the crystalline silicon bottom cell which is not covered by the perovskite top cell; the bonding strip is divided into a first bonding section and a second bonding section; the first bonding section is positioned on the upper surface of the active region; the second bonding section is located on the upper surface of the non-active region or the upper surface of the non-active region and the upper surface of a cell spacer region extending along the width direction of the cell; the welding strip is connected with the battery piece through the bonding strip. According to the cell interconnection structure, the problem of delamination of the cell piece and the welding strip is solved, and the mechanical stability of the perovskite cell is enhanced.

Capacitor structures that include a cell metal-insulator-metal (MIM) stack within topographic cell containers and cell interconnects that couple the MIM stack of a plurality of cells in electrical parallel to shared capacitor terminals. A first cell interconnect of a first conductive material may span an area under a plurality of the cell containers and a second conductive material of the MIM stack that is confined as a liner of the cell containers is in contact with the first cell interconnect, thereby reducing an electrical resistance of a first shared capacitor electrode. An insulator and another conductive material of the MIM stack is formed within the plurality of cell containers. A second cell interconnect of another conductive material may span an area over a plurality of the cell containers to further couple the MIM stacks of a plurality of cells in electrical parallel to another shared capacitor terminal.

The invention relates to a three-terminal laminated solar cell, a module and a preparation method of the three-terminal laminated solar cell, the cell comprises a bottom cell and a top cell, the bottom cell comprises a semiconductor substrate, the backlight side of the semiconductor substrate is provided with a first semiconductor region and a second semiconductor region which are opposite in conduction type, one of the first semiconductor region and the second semiconductor region has the same conductive type as the semiconductor substrate, the first electrode is conductively connected with the first semiconductor region, the second electrode is conductively connected with the second semiconductor region, and a third electrode is arranged on the backlight side of the semiconductor substrate; the top cell comprises a photoelectric conversion layer and a transparent conductive layer on a light receiving side; the conductive member extends along the lamination direction of the top cell and the bottom cell and conductively connects the transparent conductive layer and the third electrode. According to the invention, by utilizing the characteristic that the positive and negative wiring terminals of the back-contact bottom cell are both on the back, the top electrode is led to the back of the bottom cell through the conductive member, and the three wiring terminals of the cell are all arranged on the backlight side of the cell, so that the laminated cell interconnection structure is simplified.

The invention relates to the field of chip design, in particular to an interconnection system based on double-layer topology, the system comprises at least one switch and at least one interconnection topology, each interconnection topology comprises N physical topologies and a plurality of logical topologies; wherein the switch is used for connecting all the computing units in the interconnection topology. Wherein the plurality of logical topologies are obtained by configuring the switch, each logical topology comprises two unit groups and a logical path between the two unit groups, the ith logical topology comprises T logical paths, each logical path is used for connecting two computing units belonging to the two unit groups, and the T logical paths are used for connecting the two computing units belonging to the two unit groups. Different logic paths are connected with different computing units. By means of the method, the two unit groups can be interconnected through the logical topology, and the purposes of expanding the interconnection scale of the computing units, increasing topology redundancy and improving system reliability are achieved.

The invention relates to a method for interconnecting battery units of a battery system, wherein, when all battery units are on the same open-circuit voltage curve (LK, ELK), the battery units are interconnected at the same state of charge (SOC), wherein otherwise, when charging the battery units, the battery units are first interconnected at a discharge open-circuit voltage (OCVEL) and the battery units not on the same open-circuit voltage curve (LK, ELK) are disconnected when a charging open-circuit voltage (OCVL) is reached, wherein the remaining battery units are then interconnected and charged at the same state of charge (SOC), wherein, when discharging, the battery units are interconnected at a minimum SOC delta (ΔSOC) and a minimum OCV delta (ΔOCV) between the battery units.

The utility model discloses a battery cell interconnection structure in a battery module. The structure comprises a supporting frame and a plurality of battery cells, the supporting frame is composed of an upper supporting part and a supporting frame, and a containing space is formed and used for containing the battery cells. The battery cells are arranged in at least one row, the tabs are arranged in a staggered manner, and the tabs of the adjacent battery cells are staggered in position and different in polarity. The tabs can be welded with the conducting strips in parallel in an attached mode through bending, and the conducting strips are made of copper, aluminum or alloy thereof and can be connected in a laser welding mode, a resistance welding mode, an ultrasonic welding mode or a screw locking mode. The structure has the advantages of being high in welding stability, excellent in heat dissipation performance, suitable for various battery cell thicknesses, simple and convenient to assemble and the like, can effectively improve the reliability, mechanical strength and safety of the battery module, and is suitable for various battery application scenes.