19 results about "Cell interconnection" patented technology

An apparatus includes an interconnect assembly configured to receive and retain multiple batteries. The interconnect assembly includes a retainer configured to receive portions of the batteries and a conductive interconnect layer carried by the retainer. The conductive interconnect layer includes a first layer of conductive material having a first thickness and a second layer of conductive material having a second thickness less than the first thickness. The first and second layers of conductive material are attached together to form the conductive interconnect layer. The second layer of conductive material includes multiple interconnects configured to be coupled to cathodes and anodes of the batteries.

This application discloses a delay prediction method, apparatus, device, and storage medium. The delay prediction method includes: acquiring the unit characteristic information of each unit in a circuit and the characteristic sequence of each unit's interconnection; calculating the equivalent capacitance value of the interconnection path between units based on the capacitance and resistance values ​​of each unit's interconnection, and determining the target interconnection delay characteristics between units based on the equivalent capacitance values; determining the unit delay characteristics of each unit based on the equivalent capacitance values ​​and unit characteristic information; inputting the interconnection delay characteristics and unit delay characteristics into a preset delay prediction model; and performing prediction processing on the interconnection delay characteristics and unit delay characteristics based on the delay prediction model to obtain the delay result of the circuit. This application equates the capacitance and resistance values ​​of each unit's interconnection to equivalent capacitance values, overcoming the deficiency in related technologies where the load capacitance ignores the resistance shielding effect, thereby reducing the error of the load capacitance and improving the accuracy of timing prediction.

A system with a switching device is presented. The switching device includes first ports which interconnect first processing units in a first group using a first protocol and includes second ports which interconnect the first processing units with second processing units amongst second groups using the first protocol in conjunction with a second protocol. The switching device includes a switching fabric which determines a destination of an incoming data unit. If the destination is determined to be a first processing unit in the first group, the switching fabric forwards the data unit to a first port of the first ports using the first protocol. If the destination is determined to be a second processing unit in a second group of the second groups, the switching fabric forwards the data unit to a second port of the second ports using the first protocol in conjunction with the second protocol.

This invention discloses an adaptive dual-mode direction backtracking system based on double frequency conversion, comprising a radio frequency (RF) circuit, a control circuit, a local oscillator (LOO), and an antenna array. The RF circuit amplifies, filters, and mixes the RF signals received by the antenna array to form signal transmission links in mixed-mode and Van Atta array modes. The control circuit provides unified control over the RF switches and the transmit / receive delays of each channel, and outputs control signals according to the operating mode switching requirements. The LEO generates and distributes a fixed LEO signal and an adaptive LEO signal to achieve frequency matching under different incoming wave frequencies. The antenna array receives external incoming wave signals and transmits direction backtracking signals, employing an adjacent transceiver unit interconnection method in mixed-mode and a centrally symmetrical array element interconnection method in Van Atta array mode. This invention enables stable direction backtracking under different incoming wave frequencies and different application scenarios.

The invention relates to a wiring parameter determination method and device for a large-size substrate and computer equipment. The method comprises the following steps: acquiring a simulation wiring model of a large-size substrate and process technical data of the large-size interconnection substrate, and identifying each abnormal wiring area in the large-size interconnection substrate; obtaining an optimized wiring parameter of each abnormal wiring area based on the wiring parameter of each unit interconnection line; on the basis of the optimized wiring parameters of all the abnormal wiring areas, integrity index abnormal information of the large-size interconnection substrate is recognized through a connection line splicing integrity evaluation strategy, and new optimized wiring parameters of all the abnormal wiring areas are obtained through adjustment on the basis of the integrity index abnormal information of the large-size interconnection substrate; and iterating until all the integrity index abnormal information meets the preset signal integrity design requirement information, and extracting target wiring parameters of the large-size substrate. By adopting the method, the wiring efficiency of the large-size substrate can be improved.

A portable solar photovoltaic (PV) electricity generator module comprises a plurality of smart power slat (SPS) units, each SPS unit comprising a plurality of solar cells electrically connected together based on a specified cell interconnection design, and, at least one power maximizing integrated circuit collecting electricity generated by the plurality of solar cells. The plurality of SPS units are mechanically connected such that the SPS units can be retracted for volume compaction of the module, and can be expanded for increasing PV electricity generation by the module. The module can be used as part of an electric power supply with a maximum power point tracking (MPPT) power optimizer, storage battery and leads to connect to a load. The load can be AC or DC.

The application discloses an automatic double-pulse test system and a test method, which comprise an upper computer unit, a controller unit, a capacitor charging and discharging circuit unit, a load inductor unit, an IGBT power unit and an oscilloscope unit; the upper computer unit is interconnected with the controller unit; the controller unit is interconnected with the IGBT power unit; the control end of the controller unit is connected with the input end of the capacitor charging and discharging circuit unit and the load inductor unit; and the output end of the load inductor unit, the capacitor charging and discharging circuit unit and the oscilloscope unit is connected with the IGBT power unit. The whole operation process can be realized through the upper computer. The controller realizes full-automatic control and electrical isolation of the whole double-pulse test circuit, effectively guarantees test safety, the turn-on and turn-off resistance of the IGBT drive can be adjusted on line, operation is convenient, and test efficiency is greatly improved. The automatic double-pulse test system can meet most IGBT double-pulse test scenes, and can directly test the IGBT power module and the capacitor module by quickly connecting the modules with the system.

A data center electrical energy distribution system includes multiple AC, MV DC, and LV DC bus sections. A primary AC source connects to at least one AC bus section, while a secondary AC source connects to either an AC bus section or an MV DC bus section. Each MV DC bus section is linked to a DC source. The AC and LV DC bus sections operate as isolated islands, only connecting through MV DC bus sections. MV DC bus sections form a ring bus, interconnected via semiconductor switching units, which remain closed during normal operation.

The invention relates to a laser welding interconnection device (100) for photovoltaic cells (4) to form at least one string of photovoltaic cells (4) interconnected by connecting conductors (6), characterized in that it comprises: a deposit zone (ZD) for at least one photovoltaic cell (4) including a through-hole (O) configured to expose the front and rear faces of said at least one photovoltaic cell (4); a first laser welding unit (20) including a first laser head (20t) configured to perform at least one laser pulse on the front face; and a second laser welding unit including a second laser head configured to perform at least one laser pulse on the rear face, the first (20) and second laser welding units being located on either side of the through-hole (O). Figure 1

The application discloses a crystalline silicon cell, a photovoltaic module and a photovoltaic power generation system, and belongs to the field of ground crystalline silicon solar modules. In view of the problem that, in the prior art, local current enrichment is caused by local connection failure of cell interconnection, local high temperature is generated, the power of the module is reduced, the power generation capacity is reduced, the module is seriously burned to cause a fire, and the consequences are very serious, the application provides a crystalline silicon cell, a photovoltaic module and a photovoltaic power generation system. The crystalline silicon cell comprises silver grid lines, a substrate, a doped region and a back field, the silver grid lines on the upper layer of the doped region are divided into a plurality of regions, and the design of the grid line division reduces current enrichment on the non-failed conductive interconnection material when part of the conductive interconnection material fails. The application reduces the problem of local current enrichment caused by local connection failure of cell interconnection in the crystalline silicon photovoltaic module, and improves the safety of the photovoltaic power generation system.

The invention relates to a laser welding interconnection device (100) of photovoltaic cells (4) to form at least one chain (S) of photovoltaic cells (4) interconnected by connecting conductors (6), characterized in that it comprises: a laser welding unit (20) comprising a laser head (20t) configured to perform at least one laser shot for the local fusion of at least one connecting conductor (6) positioned on the front face (4a) or the rear face (4b) of at least one photovoltaic cell (4); and a turning unit (30), comprising a first gripping member (30p1) for gripping one of the front face (4a) or the rear face (4b), capable of pivoting through a first angle of rotation (R1) of at least 180°, and a second gripping member (30p2) for gripping the other of the front face (4a) or the rear face (4b). Figure for the abbreviation: Figure 1

Capacitor structures that include a cell metal-insulator-metal (MIM) stack within topographic cell containers and cell interconnects that couple the MIM stack of a plurality of cells in electrical parallel to shared capacitor terminals. A first cell interconnect of a first conductive material may span an area under a plurality of the cell containers and a second conductive material of the MIM stack that is confined as a liner of the cell containers is in contact with the first cell interconnect, thereby reducing an electrical resistance of a first shared capacitor electrode. An insulator and another conductive material of the MIM stack is formed within the plurality of cell containers. A second cell interconnect of another conductive material may span an area over a plurality of the cell containers to further couple the MIM stacks of a plurality of cells in electrical parallel to another shared capacitor terminal.

The invention relates to the field of chip design, in particular to an interconnection system based on double-layer topology, the system comprises at least one switch and at least one interconnection topology, each interconnection topology comprises N physical topologies and a plurality of logical topologies; wherein the switch is used for connecting all the computing units in the interconnection topology. Wherein the plurality of logical topologies are obtained by configuring the switch, each logical topology comprises two unit groups and a logical path between the two unit groups, the ith logical topology comprises T logical paths, each logical path is used for connecting two computing units belonging to the two unit groups, and the T logical paths are used for connecting the two computing units belonging to the two unit groups. Different logic paths are connected with different computing units. By means of the method, the two unit groups can be interconnected through the logical topology, and the purposes of expanding the interconnection scale of the computing units, increasing topology redundancy and improving system reliability are achieved.

The invention relates to a method for interconnecting battery units of a battery system, wherein, when all battery units are on the same open-circuit voltage curve (LK, ELK), the battery units are interconnected at the same state of charge (SOC), wherein otherwise, when charging the battery units, the battery units are first interconnected at a discharge open-circuit voltage (OCVEL) and the battery units not on the same open-circuit voltage curve (LK, ELK) are disconnected when a charging open-circuit voltage (OCVL) is reached, wherein the remaining battery units are then interconnected and charged at the same state of charge (SOC), wherein, when discharging, the battery units are interconnected at a minimum SOC delta (ΔSOC) and a minimum OCV delta (ΔOCV) between the battery units.

The utility model discloses a battery cell interconnection structure in a battery module. The structure comprises a supporting frame and a plurality of battery cells, the supporting frame is composed of an upper supporting part and a supporting frame, and a containing space is formed and used for containing the battery cells. The battery cells are arranged in at least one row, the tabs are arranged in a staggered manner, and the tabs of the adjacent battery cells are staggered in position and different in polarity. The tabs can be welded with the conducting strips in parallel in an attached mode through bending, and the conducting strips are made of copper, aluminum or alloy thereof and can be connected in a laser welding mode, a resistance welding mode, an ultrasonic welding mode or a screw locking mode. The structure has the advantages of being high in welding stability, excellent in heat dissipation performance, suitable for various battery cell thicknesses, simple and convenient to assemble and the like, can effectively improve the reliability, mechanical strength and safety of the battery module, and is suitable for various battery application scenes.

A structure is disclosed. The structure can include a first plurality of integrated device dies, an interconnect device, and an optical unit. The interconnect device can be electrically connected to the first plurality of integrated device dies. The optical unit can be disposed vertically above the interconnect device. The optical unit can be optically connected to an optical interconnect. The first plurality of integrated device dies can communicate with a second plurality of integrated device dies at least through the interconnect device, the optical unit, and the optical interconnect.

A structure is disclosed. The structure can include a first plurality of integrated device dies, an interconnect device, and an optical unit. The interconnect device can be electrically connected to the first plurality of integrated device dies. The optical unit can be disposed vertically above the interconnect device. The optical unit can be optically connected to an optical interconnect. The first plurality of integrated device dies can communicate with a second plurality of integrated device dies at least through the interconnect device, the optical unit, and the optical interconnect.

Capacitor structures that include a cell metal-insulator-metal (MIM) stack within topographic cell containers and cell interconnects that couple the MIM stack of a plurality of cells in electrical parallel to shared capacitor terminals. A first cell interconnect of a first conductive material may span an area under a plurality of the cell containers and a second conductive material of the MIM stack that is confined as a liner of the cell containers is in contact with the first cell interconnect, thereby reducing an electrical resistance of a first shared capacitor electrode. An insulator and another conductive material of the MIM stack is formed within the plurality of cell containers. A second cell interconnect of another conductive material may span an area over a plurality of the cell containers to further couple the MIM stacks of a plurality of cells in electrical parallel to another shared capacitor terminal.

A semiconductor device includes a first substrate structure including a substrate, circuit elements on the substrate in a chip region, a circuit interconnection structure on the circuit elements, a circuit test element in a test element region, a first test interconnection structure in the test element region and electrically connected to the circuit test element, and first bonding pads on the circuit interconnection structure and the first test interconnection structure, and a second substrate structure on the first substrate structure. The second substrate structure includes gate electrodes, a channel structure penetrating the gate electrodes, a cell interconnection structure electrically connected to the channel structure and the gate electrodes, a cell test element in the test element region, a second test interconnection structure in the test element region and electrically connected to the cell test element and electrically isolated from the first test interconnection structure, and second bonding pads.