The invention provides a
bladder capacity accelerated measurement method based on an FPGA. The method comprises the steps that a bladder ultrasonic image is obtained, left and right extreme points of the lower wall of the bladder ultrasonic image are positioned, bladder wall adduction inspection is completed, and the adduction points are merged into a boundary point array; adopting a Bresenham straight line
algorithm to set 8-bit gray values of pixel positions where all boundary points in the boundary point array are located as 255, generating a closed bladder area contour, and packaging a bladder area contour detection
algorithm into an
edge detection IP core; based on the
edge detection IP core, a lightweight U-Net capacity measurement IP core is adopted to carry out capacity measurement; wherein the lightweight U-Net is an optimized U-Net network, and comprises the steps of performing spatial selective suppression on a feature map extracted by the U-Net network by adopting pixel information based on a bladder contour in a bladder
ultrasound image, introducing residual connection to a jump connection part, enhancing gradient flow and suppressing artifacts; in the process of measuring the
bladder capacity, end-to-end
bladder capacity measurement is completed by combining an input channel, an output channel and a pixel parallel three-dimensional calculation structure of a
network model; according to the method, dynamic threshold calculation based on the local neighborhood of the core point and an extreme point screening rule are combined, and the problem that a traditional
algorithm is easily interfered by ultrasonic
noise and surrounding tissues is solved.