This invention relates to the field of
quantum-resistant computing and
cryptography, and discloses a hardware-accelerated parallel implementation method and
system for
quantum-resistant
digital signature algorithms. The method includes: mapping a private key matrix to the conductance states of a resistive-switched non-
volatile memory array; converting the message to be signed into an input vector and loading it into a row-driven circuit; performing matrix-vector multiplication in situ using the
memory array, with the operational current obtained by a column-sensing circuit; performing analog-to-
digital conversion, post-
processing, and rejection sampling judgment on the current, and outputting the signature result. The
system includes a central control module, a resistive-switched memory computing core array, a row-driven circuit module, a column-sensing and conversion module, and a post-
processing operator cluster. By adopting the above technical solution, this invention can achieve high-performance, low-power, and low-latency
parallel processing of
quantum-resistant digital signatures, improving
throughput and enhancing deployment feasibility in edge and mobile devices.