Furnishings, comprehensive: Processor pipeline switching logic (220 - 260) configured to perform operations on register
operand data, wherein the processor pipeline switching logic (220 - 260) includes a decode switching logic (230) configured to decode instructions for execution;
Memory hierarchy switching logic (845) configured to provide memory support for register
operand data in one or more cache circuits (210, 670, 685); and Blocking logic (215) configured to: Controlling a first set of lock indicators for a set of registers for a first thread, including acknowledging one or more lock indicators for registers indicated by the decoding circuit (230) as being used by decoded instructions of the first thread; Storing register
operand data in one or more cache circuits (210, 670, 685), including preventing the removal of a given cache row from a cache circuit of the one or more cache circuits (210, 670, 685) based on an affirmed lock indicator, wherein the affirmed lock indicator applies to a register for which operand data is stored in the given cache row; and Clearing the first set of lock indicators in response to a reset event.