57results about How to "Adversely affected" patented technology

A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system wherein the address translation data entries are stored in one or more data structures / tables in the hierarchy, one or more of which can be updated in-place multiple times without having to overwrite data. This hierarchal address translation data structure and multiple update of data entries in the individual tables / data structures allow the hierarchal address translation data structure to be efficiently stored in a non-volatile memory array without markedly inducing write fatigue or adversely affecting the lifetime of the part. The hierarchal address translation of embodiments of the present invention also allow for an address translation layer that does not have to be resident in system RAM for operation.

Systems and methods are described for hybrid spread spectrum radio systems. A method, includes receiving a hybrid spread spectrum signal including: fast frequency hopping demodulating and direct sequence demodulating a direct sequence spread spectrum signal, wherein multiple frequency hops occur within a single data-bit time and each bit is represented by chip transmissions at multiple frequencies

Systems and methods are described for hybrid spread spectrum radio systems. A method includes modulating a signal by utilizing a subset of bits from a pseudo-random code generator to control an amplification circuit that provides a gain to the signal. Another method includes: modulating a signal by utilizing a subset of bits from a pseudo-random code generator to control a fast hopping frequency synthesizer; and fast frequency hopping the signal with the fast hopping frequency synthesizer, wherein multiple frequency hops occur within a single data-bit time.

A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system wherein the address translation data entries are stored in one or more data structures / tables in the hierarchy, one or more of which can be updated in-place multiple times without having to overwrite data. This hierarchal address translation data structure and multiple update of data entries in the individual tables / data structures allow the hierarchal address translation data structure to be efficiently stored in a non-volatile memory array without markedly inducing write fatigue or adversely affecting the lifetime of the part. The hierarchal address translation of embodiments of the present invention also allow for an address translation layer that does not have to be resident in system RAM for operation.

In an actuator (1) in which an angle detector (13) of a magnetic encoder for detecting the rotational position of a motor (3) is incorporated inside a wave reduction gear (5), detection signals from Hall elements (11a, 11b) of the angle detector (13) are transmitted via sensor lead wires (17) that have been brought out through wiring holes (36a, 33a, 35a, 37a) formed inside the motor (3) to a sensor signal converter board (14) disposed on the rear end side of the motor. Since the wiring is not required to be brought out to the exterior, indirectly routed along the exterior of the motor (3), and brought out to the rear side thereof, the wiring is not mechanically damaged and can be brought out with the shortest possible wiring distance, and the effect of electromagnetic noise can be reduced.

It is possible to achieve compatibility between suppressing dark current caused by a leak phenomenon and ensuring element reliability in a CMOS solid-state imaging device. When a pixel using electrons as signal charge is driven, the negative voltage level of each of control signals adapted to pulse-drive transistors in the pixel is adjusted so that the longer the charge accumulation time, the higher the voltage level. Preferably, the negative voltage level is grounded (GND) when no signal charge is accumulated. The negative voltage level is increased only when the charge accumulation time is long, which is the case where dark current caused by a leak phenomenon becomes a problem. Therefore, it is possible to suppress stress on the pixels and the gate oxide film of their drive circuits and degradation of the transistor characteristics even if dark current is suppressed.