55 results about "Allocator" patented technology

The invention discloses a reconfigurable systolic array tensor IP core based on an FPGA. The architecture comprises a core controller, a shift distributor, a data processing array and a four-stage data cache. The tensor core can adapt to general tensor multiplication and addition operations in Prefill and Decode stages of the generative neural network at the same time through reconfigurable design. The core controller receives the tensor multiplication instruction and the configuration information and decouples the tensor multiplication instruction and the configuration information according to a data stream to generate a plurality of block tensor multiplication instructions. The shift distributor decodes a block tensor multiplication instruction, decoded mode information controls data communication between a first-level cache and a second-level cache (Distrided RAM and Bram), a control signal of a data processing array is generated, and the control signal enters the array together with data to flow. And the data processing array is connected with different secondary BRAM caches according to the received configuration information and is used for processing data in a bubble-free pulsating flow manner. The four-stage data cache realizes the multi-stage pinpong operation of the loading of the operation data of the tensor operation core, and realizes the multi-stage pipeline design of the data from the off-chip HBM to the on-chip URAM, from the URAM to the BRAM and from the BRAM to the operation unit. Aiming at a single-user edge end generation type network reasoning task, a core controller generates a data processing unit mode configuration signal in a fine-grained (tensor element level) manner, and the data processing unit mode configuration signal is transmitted by a shift distributor and flows in parallel with operation data, so that the mode configuration efficiency and the hardware resource utilization rate are greatly improved, the problem of high fan-out caused by broadcast control is reduced, and the user experience is improved. A control flow is designed by means of the structural characteristics of the systolic array, and a complex control algorithm is realized with low resource occupation.

The invention provides a memory block management method and a controller. The method comprises the following steps: acquiring a configuration file in a Linux kernel, analyzing the configuration file to obtain a memory size interval, determining a use state of a memory block in the memory size interval, and setting a bit flag of the use state in a flag bit corresponding to each memory block; whether the memory size of a target memory block of the current allocation request is in a memory size interval or not is judged, if yes, whether a first idle linked list in the SLUB allocator is empty or not is judged, and the first idle linked list is used for storing the flag bit of the memory block with the bit marked as idle; and if not, sequentially selecting a flag bit of a target memory block of a linked list from a first idle linked list of the SLUB allocator, and determining the target memory block for the current allocation request according to the flag bit of the target memory block. According to the method and the device, the problems of too high memory block metadata occupation and low allocation efficiency in the SLUB allocator can be solved.

The invention relates to a GPU memory access simulation system and method, a storage medium and electronic equipment. The GPU memory access simulation system comprises a GPU multi-thread simulation module, a page calculation module, a shared lock dynamic distributor and a GPU memory module. The page calculation module is configured to respond to a memory access request initiated by any thread in the GPU multi-thread simulation module and determine an accessed memory page based on the memory access request; and the shared lock dynamic allocator is configured to allocate one or more locks corresponding to the accessed memory pages to each thread based on the accessed memory pages corresponding to the memory access requests of each thread, so that all the threads initiating the memory access requests can access the GPU memory module according to the respective allocated locks. According to the method, one or more locks corresponding to the accessed memory pages are respectively allocated to each thread based on the accessed memory pages corresponding to the memory access requests of each thread through a shared lock dynamic allocation mechanism, so that the simulation efficiency of GPU memory access simulation is improved.

A method of serving a generative transformer model includes determining a batch size to use in processing inference requests and allocating at least one prompt pipeline and at least on token pipeline to the generative transformer model to process the batch of inference requests. The number of prompt pipelines and the number of token pipelines, and the depths of the pipelines are determined based on the batch size, an average prompt length, a cache requirement per stage, and a memory footprint of model weights for the generative model per stage using a resource allocator component of the model serving system. Cache streaming is used to stream prompt cache from prompt pipelines to token pipelines to generate tokens. Cache streaming involves gather-copy operations which may be performed using compute kernels.

The invention provides a resource management method and device based on combination of a Slab distributor and a Buddy system, and relates to the technical field of computers.The method comprises the steps that firstly, the Buddy system composed of a plurality of linked lists (recording the initial position of an index interval, the interval length and the use state) is constructed; the method comprises the following steps: distributing continuous index intervals from a Buddy system to construct a Slab cache region; when a resource request is received, searching and distributing available index units in the Slab cache region through the Slab distributor; if not, calling the Buddy system to distribute a new continuous index interval, and constructing a new Slab cache region based on the interval; and after the index units are released, if all the index units in the corresponding Slab cache region are released, returning the index interval corresponding to the Slab cache region to the Buddy system. While the MTT resources are quickly allocated and recycled, fragments are effectively reduced, and the resource utilization rate and the system response speed are improved.

Systems and methods for an eBPF general allocator for an eBPF program is provided. The method includes receiving, by a first eBPF program, a first entry based on an atomic operation. The first entry is from a number of entries in a free list that indicates available space in a buffer. The available space is indexed by the number of entries in the free list. The method further includes identifying, based on the first entry, a pointer to the buffer. The pointer is associated with an allocation of the available space in the buffer based on the first entry. The allocation of the available space is to the first eBPF program. The method further includes executing, by a processing device, the first eBPF program with exclusive access to the allocation of the available space in the buffer during an execution instance of the first eBPF program.

A method and apparatus for dynamically allocating resources for quality of service (QoS) aware and high-efficient workload consolidation in a multi-instance disaggregated memory system include, using a resource allocator, allocating resources to a latency-critical (LC) application and a batch application included in an application server based on a current system state determined at a preset interval, using a performance monitor, collecting performance data of the LC application and the batch application to which the resources are allocated, using a system state space explorer, exploring a system state based on the collected performance data of the LC application and the batch application, and based on the exploration of the system state, determining a subsequent system state expected to have improved throughput compared to throughput based on the current system state or satisfy the QoS.

The invention provides a memory access method, a memory, a storage medium and electronic equipment. The memory access method comprises the following steps: uniformly distributing a target Bank number for an operation request by a Bank number distributor; the intelligent scheduling arbiter judges whether the operation requests corresponding to the same Bank have read-write conflicts or not based on the target Bank numbers of the operation requests; when it is determined that the operation requests corresponding to the same Bank have read-write conflicts, the intelligent scheduling arbiter stores one or more operation requests in the queue in a multi-input multi-output register based on CSR setting; and the intelligent scheduling arbiter controls the execution sequence of the operation requests in the queue and the operation requests in the multi-input multi-output register. Through the method, read-write conflicts for the same Bank can be avoided, global dynamic priority setting is supported, the output bandwidth of a memory is fully utilized, and the processing efficiency of data requests is improved.

A method of core allocation for temperature control in under-subscribed computing systems can include maintaining, by an allocator component, a virtual to physical core mapping of physical cores of a computing system; identifying a change to a next core allocation according to an allocation pattern; determining a time that a process of a software application can be moved to the next core allocation, wherein the process of the software application is configured with core pinning; and updating, by the allocator component, the virtual to physical core mapping for the process of the software application at the determined time. The allocator component can intercept a process request of the software application; identify a pinned core of the process request; and overwrite the pinned core of the process request with an allocated core indicated by the virtual to physical core mapping.

The invention discloses a real-time compiling method and device, equipment and a storage medium, belongs to the field of data processing, and can solve the problem that a program cannot be compiled on a target platform in real time. The method comprises the following steps: converting source codes in a character stream into a symbol set through a lexical analysis state machine; processing the grammar symbols in the symbol set through an analysis engine to generate corresponding intermediate representations; the intermediate representation is processed through an assembly generator and a node distributor, a binary file corresponding to a target platform is obtained, and the binary file at least comprises a first machine instruction corresponding to the target platform; and compiling the dynamic code through a real-time compiling engine to obtain a second machine instruction corresponding to the target platform, and putting the second machine instruction into a dynamic loading library to load and run the second machine instruction.

The present invention discloses a method, device and product for constructing an efficient and scalable federated learning system based on P2P. First, the parameter server selects the client based on historical information such as statistical efficiency, processing speed, and distribution contribution, and the client allocator assigns a dedicated executor to the selected client. The executor runs in an isolated container environment, conducts real communication through a dedicated network card, and distributes the global model using a P2P communication library; the executor sends the training configuration, local data set, and global model to the computing node, and the computing node returns the model update to the executor after several rounds of local training; the parameter server receives the model update from the executor and generates a new global model. The present invention optimizes model distribution through P2P communication and designs a client selection scheme that comprehensively considers multiple historical information. In addition, FedP2P builds a high-fidelity simulation platform to accurately simulate the computing and communication behaviors in actual federated training, thereby verifying the effectiveness of the scheme design.

A dynamic data extraction, distillation, and enhancement system is disclosed that includes a dynamic extraction, distillation, and enhancement framework. The framework includes an allocator, extractor, and deconstructor stored in a non-transitory memory that, when executed by a processor, receive files in different formats from data sources, determine a native format of each file, identify and extract an embedded object from a file, deconstruct the file into components, assign each file to one of a plurality of streams based on the native format of the file, assign the embedded object to a stream based on a format of the embedded object, and assign a deconstructed component to a stream based on a format of the deconstructed component. The native format includes one of text, video, image, or audio. Each stream corresponds to one native format. The streams include a text stream, an audio stream, a video stream, and an image stream.

The invention provides a memory device. A memory device includes a memory block, an operation processor, and an address allocator. The memory block includes a plurality of string groups connected to a plurality of word lines. The operation processor is configured to set a program operation mode of the memory block to one of a single-layer cell (SLC) mode and a multi-layer cell (MLC) mode in response to a command received from outside the memory device. The address allocator is configured to allocate row addresses of the memory blocks differently according to a program operation mode.

A method in a computing device includes: obtaining schedule data for a facility, the schedule data including a plurality of segments, each segment having (i) a start time, (ii) an end time, and (iii) a worker identifier assigned to the segment from a plurality of worker identifiers; obtaining presence data including, for each of the plurality of worker identifiers, whether a corresponding worker is present at a facility; detecting, from the presence data, a worker present at the facility, having a first worker identifier that is not assigned to any of the segments in the schedule data; generating an auxiliary segment having (i) a start time based on the presence data, (ii) an end time based on a comparison of the schedule data with the presence data, and (iii) the first worker identifier; and providing the auxiliary segment to a task allocator with the schedule data.

Techniques of a system operable to allocate physical pages of memory are described. The system may include a memory - side cache, a memory - side cache monitoring unit coupled to the memory - side cache, and an operating system (OS) page allocator. The OS page allocator may receive feedback from the memory - side cache monitoring unit. The OS page allocator may adjust a page allocation policy based on the feedback received from the memory - side cache monitoring unit, where the page allocation policy defines the physical pages allocated by the OS page allocator.

The invention relates to a multi-task convolutional neural network architecture applied to an advanced driving assistance system, and the architecture comprises a batch processor which is used for merging data sets of a plurality of perception tasks from the advanced driving assistance system and outputting a merged data batch; the multi-task model is used for performing feature extraction on the merged data batches to extract shared features, fusing the shared features based on an attention mechanism and then outputting multiple tasks; and the task distributor is used for performing task configuration and loss weight adjustment on the multiple tasks. According to the invention, a plurality of sensing tasks can be processed in parallel, and the calculation efficiency and performance can be improved to the greatest extent.

A programming assisting program causes a computer to function as a calculator that acquires, from a database storing information indicating an address space in a memory having a range pre-allocated to each type of component included in a project performed by a PLC, the information indicating the address space, and allocates components to the address space to calculate a use volume in the memory used by the project for each type of component, a determiner that determines, based on the use volume and an allocated volume in the memory determined based on the pre-allocated range, an allocated volume allocated to each type of component, a changer that changes, based on the determined allocated volume for each type of component, the range pre-allocated to each type of component, and a display that displays, for each type of component, the calculated use volume and the determined allocated volume on a screen.

The application relates to a resource allocation system, method, device, computer equipment and storage medium. The system comprises an allocator configured to determine a resource container corresponding to a resource allocation request, and determine a target resource identifier corresponding to the resource container from a candidate resource identifier set; a resource plug-in configured to trigger, in response to an allocation instruction message, establishment of a resource association relationship of a resource container corresponding to the target resource identifier and a container identifier; and a resource container configured to acquire, in a business processing process, the target resource identifier according to the resource association relationship, determine a target installation position corresponding to the target resource identifier according to a position correspondence relationship, and call a target business processor installed in the target installation position to process business data. According to the above scheme, even if the business processor in the target installation position is replaced, the resource container can still call a new target business processor to process business, so that the order of resource use can be ensured, and the use efficiency of computing resources is improved.

The application relates to the technical field of artificial intelligence, and discloses an information computing load scheduling method, device and equipment under an Internet of Things mode and a medium, which comprises the following steps: receiving an information computing task, distributing the information computing task to a corresponding target execution container; generating a priority queue of the information computing task in each target execution container; controlling the computing resource allocation proportion of each target execution container through a pre-trained resource allocator; and adjusting the execution order of an execution task according to the state of the execution task in the priority queue through a pre-trained execution scheduler. The application realizes full utilization of platform computing resources, reduces the weighted average execution time of the task priority, and improves user satisfaction.

This invention discloses a method, apparatus, device, and medium for dynamic library mapping execution in binary translation, comprising: translating and executing the instructions of an x86 executable program; determining whether it is a dynamic library function call instruction; if it is a dynamic library function call instruction, parsing the call instruction to obtain the called function; using the called function as a lookup index key to query a pre-established dynamic library mapping allocator to obtain a first value and a second value corresponding to the function in the RISC-V dynamic library; determining the starting address of the RISC-V dynamic library in memory, and using the first value as an offset value to calculate the absolute address of the function in memory; determining the parameter address of the function based on the second value; performing calculations on the function using the parameter address and the absolute address, and returning the calculation result. This reduces the system overhead during the translation process.

This invention discloses an allocator, a memory allocation and release method for optimizing the jitter performance of dynamic memory allocation. The allocator includes a heap memory partitioning module, a round-robin allocation scheduling module, a memory allocation execution module, and a memory release module. The memory allocation method divides the available heap memory of the real-time operating system into several independent memory pools. After receiving an allocation request, it selects the target memory pool based on a round-robin counter and performs the allocation. The memory release method determines the memory pool based on the memory pointer and returns the memory block to the corresponding free data structure. This invention improves system throughput and concurrency by distributing allocation requests through multiple independent memory pools combined with round-robin scheduling. Round-robin scheduling has O(1) deterministic time overhead, stabilizes allocation time, and accurately defines the worst-case execution time, meeting the deterministic requirements of real-time systems. The memory pools achieve physical isolation of data structures, reducing access latency.

The invention discloses a dynamic library mapping execution method and device in binary translation, equipment and a medium. The method comprises the steps that translation execution is conducted on an instruction of an X86 executable program, whether the instruction is a dynamic library function calling instruction or not is judged, and when the instruction is the dynamic library function calling instruction, the calling instruction is analyzed, and a called function is obtained; querying in a pre-established dynamic library mapping distributor by taking the called function as a query index key to obtain a first value and a second value corresponding to the function in the RISC-V dynamic library; determining a first address of the RISC-V dynamic library in the memory, and calculating to obtain an absolute address of the function in the memory by taking the first value as an offset value; determining a parameter address of the function according to the second value; and calculating the function by using the parameter address and the absolute address, and returning a calculation result. And the system overhead in the translation process is reduced.

A central processing unit (CPU) is disclosed. The CPU includes: a physical register file (PRF) including a plurality of physical registers; an instruction queue configured to store an instruction identifying an opcode, a source operand register, and a destination operand register; and an allocator, configured to allocate a first physical register to the destination operand register, where the first physical register has a first changeable bit size corresponding with a result bit size of the destination operand register.

Provided are systems, methods, and apparatuses of program execution in a processing element (PE). In one or more examples, the systems, devices, and methods include executing software code at a processing element (PE) of a stacked memory module; pushing, via a dispatcher of the PE, a first command of the software code from a submission queue to a first dispatch queue, the PE comprising multiple dispatch queues that include the first dispatch queue; pushing, via the dispatcher, a barrier command of the software code from the submission queue to the first dispatch queue; holding a second command of the software code at the submission queue based on the barrier command; and pushing the second command from the submission queue to the first dispatch queue based on the dispatcher determining that the first dispatch queue is empty.

This invention discloses a storage system, read / write method, and controller for reducing file fragmentation, belonging to the field of data storage technology. The system includes a host and a solid-state drive (SSD). The host has a file system and a space pre-allocator, while the SSD has a segment allocator. The file system allocates logical address space to files according to segments. The segment allocator maintains a global translation table, which records the mapping relationship between segment IDs and mapped page addresses. The mapped pages are flash pages used to record the logical page addresses within a segment to the physical page addresses. The segment allocator also calculates free segment IDs in a monotonically increasing manner and publishes them to the circular buffer when there is remaining space. The space pre-allocator retrieves the free segment ID from the head of the circular buffer and allocates it to the file when space needs to be allocated. This invention can reduce the generation of file fragmentation and free space fragmentation in the file system, improving the overall performance and stability of the system.

The invention provides a virtual machine linear memory expansion method and device, a storage medium and electronic equipment, and is applied to the technical field of virtual machine memories. When the application program is started, the software development kit is initialized, and the preset capacity of the memory linear distributor of the corresponding system version is obtained. And analyzing the memory mapping file of the SDK, determining a memory area range, and calling a local method to find a memory initial address. And according to the address, expanding a memory linear allocator, and allocating a target buffer area by utilizing a memory mapping function. According to the method, the memory capacity is improved, the problem of limitation of the number of virtual machine methods is effectively solved, stable operation under all scenes including dynamic loading during starting and operation is ensured, and therefore the situations of collapse and installation failures are reduced.

The invention provides an alarm computing load balancing method, which belongs to the technical field of cloud computing and distributed monitoring operation and maintenance, adopts a distributed architecture, and comprises a plurality of Prometheus examples, a scheduling management module, a task distributor, an equal division algorithm executor and a shared storage component. The scheduling management module dynamically fragments the alarm rules according to rule types, data source features or time dimensions, and adjusts the number and size of fragments according to real-time loads. And the equal division algorithm executor combines the load, the performance index and the resource utilization rate of each instance, adopts strategies such as consistent Hash, polling or weighted polling to calculate an assignment relationship, and supports newly-added rule allocation and fragment migration. Dynamic management and real-time synchronization of rules are achieved through the shared storage component, stateless deployment of Prometheus instances is achieved, requests are distributed through the load balancer, and therefore the load balancing capacity, the rule management efficiency and the alarm timeliness are improved.

The invention discloses a storage system capable of reducing file fragments, a read-write method and a controller, and belongs to the technical field of data storage, the system comprises a host and a solid state disk, a file system and a space pre-distributor are created in the host, and a segment distributor is arranged in the solid state disk; the file system allocates a logic address space for the file according to segments; the segment distributor is used for maintaining a global translation table, the global translation table is used for recording a mapping relation from a segment ID to a mapping page address, and the mapping page is a flash memory page used for recording a logic page address to a physical page address in the segment; the segment distributor is further used for calculating idle segment IDs in a monotone increasing mode and issuing the idle segment IDs to the ring buffer area when the ring buffer area has residual space; and the space pre-distributor is used for taking out the idle segment ID of the head of the annular buffer area and distributing the idle segment ID to the file when the space needs to be distributed to the file. The generation of file fragments and free space fragments in the file system can be reduced, and the overall performance and stability of the system are improved.

The present application discloses a shared memory management method and cache service component, wherein the cache service component includes: a cache allocator and a data item queue manager; the cache allocator is used to allocate and release virtual memory; the data item queue manager is used to record the location of data in the cache allocator in the virtual memory and the total size of the data items; the cache allocator includes: a first header area and a data area, the first header area is used to record the offset and size of the allocated virtual memory, the data area includes multiple equally divided memory blocks, the memory blocks are used to record the data placed in the virtual memory; the data item queue manager includes: a second header area and an element area, the second header area is connected to the element area, the element area includes a circular queue, the circular queue is used to record the starting offset and total size of the data items, and the second header area is used to record the characteristic information of the circular queue. The present application discloses a technical solution that can independently save images and is simple to operate and easy to maintain.

The present invention provides a hardware lookup table for an artificial intelligence chip, a method for loading data, and a computing device, the device comprising: a memory group, the memory group comprising a plurality of storage units, each storage unit having a storage space corresponding to the input data of the hardware lookup table; a data distributor, for distributing the input data of the hardware lookup table to the corresponding storage unit; a readout module, for reading data from the corresponding storage unit according to the address lookup data, wherein the bit width of the input data of the hardware lookup table is the same as the data bus bit width of the artificial intelligence chip. The technical solution according to the present invention can shorten the lookup table loading time, improve the lookup table performance, and reduce power consumption.