35results about How to "Improving yield and reliability" patented technology

The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof and provides a chip embedded printed circuit board including: an insulating layer having vias formed therethrough; a first chip and a second chip embedded in the insulating layer and having pads, which are respectively exposed to upper and lower surfaces of the insulating layer, on one surfaces thereof; an upper pattern formed on the upper surface of the insulating layer to be connected to the pads of the first chip and the vias; and a lower pattern formed on the lower surface of the insulating layer to be connected to the pads of the second chip and the vias. Also, the present invention provides a manufacturing method of a chip embedded printed circuit board.

A method of defect review. First, a wafer with a plurality of defects is provided. A defect inspection is performed to detect the defects. An automatic defect classification is then performed to divide the defects into different defect types according to a predetermined database. A defect review is performed to review different defect types of defects which are sampled in different weights according to yield killing ratios of each defect types.

A method of defect review. First, a wafer with a plurality of defects is provided. A defect inspection is performed to detect the defects. An automatic defect classification is then performed to divide the defects into different defect types according to a predetermined database. A defect review is performed to review different defect types of defects which are sampled in different weights according to yield killing ratios of each defect types.

A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.

A high-purity copper sputtering target, wherein a Vickers hardness of a flange part of the target is in a range of 90 to 100 Hv, a Vickers hardness of an erosion part in the central area of the target is in a range of 55 to 70 Hv, and a crystal grain size of the erosion part is 80 μm or less. This invention relates to a high-purity copper sputtering target that does not need to be bonded to a backing plate (BP), and aims to provide a high-purity copper sputtering target capable of forming a thin film having superior uniformity by enhancing a strength (hardness) of the flange part of the target, and reducing an amount of warpage of the target. Moreover, the uniformity of the film thickness is improved by adjusting the (111) orientation ratio of the erosion part and the flange part in the target. The present invention thereby aims to provide a high-purity copper sputtering target, which is capable of improving the yield and reliability of semiconductor products that are being subject to further miniaturization and higher integration, and useful for forming a copper alloy wiring for semiconductors.

Provided are a molecular electronic device and a method of fabricating the molecular electronic device. The molecular electronic device includes a substrate, an organic dielectric thin film formed over the substrate, a molecular active layer formed on the organic dielectric thin film and having a charge trap site, and an electrode formed on the molecular active layer. The organic dielectric thin film may be immobilized on the electrode or a Si layer by a self-assembled method. The organic dielectric thin film may include first and second molecular layers bound together through hydrogen bonds. An organic compound may be self-assembled over the substrate to form the organic dielectric thin film. The organic compound may include an M′-R-T structure, where M′, R and T represent a thiol or silane derivative, a saturated or unsaturated C1 to C20 hydrocarbon group which is substituted or unsubstituted with fluorine (F), and an amino(—NH2) or carboxyl (—COOH) group, respectively.

A chip package structure includes a circuit substrate, a chip, at least one bonding wire, and an adhesive layer. The circuit substrate has a bonding surface and at least one pad disposed on the bonding surface. The chip is disposed on the bonding surface of the circuit substrate and has an active surface away from the circuit substrate and at least one contact pad disposed on the active surface. The bonding wire is connected between the contact pad and the pad, such that the chip is electrically connected to the circuit substrate through the bonding wire. The bonding wire includes a copper layer, a nickel layer covering the copper layer, and a gold layer covering the nickel layer. The adhesive layer is disposed between the pad and the bonding wire and between the contact pad and the bonding wire and respectively covers two terminals of the bonding wire.

A power module is disclosed. The power module includes a carrier board, two switches, at least one metal block, a clamping component and a metal conductive component. The carrier board includes an upper surface and a lower surface. The two switches are disposed on the upper surface and connected in series to form a bridge arm electrically connected between a positive terminal and a negative terminal. The metal block is electrically connected to the two switches. The clamping component is disposed on the upper surface and electrically connected in parallel with the bridge arm through the carrier board. The metal conductive component is connected from a common node of the two switches to an output terminal. The metal conductive component is located at a side of the two switches facing away from the upper surface.

A method for manufacturing a semiconductor device includes forming an underlying layer over a semiconductor substrate; forming a hard mask layer over the underlying layer; forming first etch patterns over the hard mask layer; forming second etch patterns between the first photoresist patterns; etching the hard mask layer using the first and second etch patterns as an etch mask to form a hard mask pattern; and etching the underlying layer using at least the hard mask pattern. The first and second etch patterns are formed on the same layer.

A carrier board and a power module using the same are disclosed. The carrier board includes a main body, two metal-wiring layers and at least one metal block. The main body includes at least two terminals and a surface. The two terminals are disposed on the surface. The two metal-wiring layers are disposed on the main body to form two parts of metal traces connected to the two terminals, respectively. The at least one metal block is embedded in the main body and connected to one of the two terminals. A thickness of the two parts of metal traces is less than that of the metal block. The two terminals connected by the two parts of metal traces have a loop inductance less than or equal to 1.4 nH calculated at a frequency greater than 1 MHz.

A power module is disclosed. The power module includes a carrier board, two switches, at least one metal block, a clamping component and a metal conductive component. The carrier board includes an upper surface and a lower surface. The two switches are disposed on the upper surface and connected in series to form a bridge arm electrically connected between a positive terminal and a negative terminal. The metal block is electrically connected to the two switches. The clamping component is disposed on the upper surface and electrically connected in parallel with the bridge arm through the carrier board. The metal conductive component is connected from a common node of the two switches to an output terminal. The metal conductive component is located at a side of the two switches facing away from the upper surface.

An RRAM structure and its manufacturing method are provided. The RRAM structure includes a bottom electrode layer, a resistance switching layer, and an implantation control layer sequentially formed on a substrate. The resistance switching layer includes a conductive filament confined region and an outer region surrounding the conductive filament confined region. The RRAM structure includes a protective layer and a top electrode layer. The protective layer conformally covers the bottom electrode layer, the resistance switching layer, and the implantation control layer and has a first opening. The top electrode layer is located on the implantation control layer, and a portion of the top electrode layer is filled into the first opening. The position of the top electrode layer corresponds to that of the conductive filament confined region, and the top surface of the top electrode layer is higher than that of the protective layer.

An embedded component structure includes a circuit board, an electronic component, a first conductive terminal, and a second conductive terminal. The circuit board includes a first electrical connection layer and a second electrical connection layer. The electronic component is embedded in the circuit board and includes a first contact and a second contact. The first conductive terminal and the second conductive terminal respectively at least cover a part of top surfaces and side walls of the first contact and the second contact, and the first electrical connection layer and the second electrical connection layer are respectively electrically connected to the first contact and the second contact through the first conductive terminal and the second conductive terminal. A method for manufacturing an embedded component structure is also provided.