13 results about "Write combining" patented technology

A compute tile includes a WCB that receives a workload of writing an output tensor of a convolution into a local memory of the compute tile. The local memory may be a SRAM. The WCB receives write transactions. A write transaction includes a data block, which is a part of the output tensor, and metadata describing one or more attributes of the data block. The WCB may store write transactions in its internal buffers. The WCB may determine whether to combine two write transactions, e.g., based on an operation mode or metadata in the write transactions. In embodiments where the WCB determines to combine the two write transactions, the WCB may combine the two write transactions into a new write transaction and write the new write transaction into the local memory or an internal memory of the WCB. The total number of write transactions for the workload can be reduced.

This invention discloses a general-purpose data partitioning hardware accelerator, tightly coupled to a processor core, for partitioning an input dataset containing multiple data records into multiple output partitions. The accelerator includes a length-aware read and distribute module and multiple parallel processing engines. The length-aware read and distribute module reads the data stream and decoupled metadata stream in parallel, parses variable-length record boundaries in real time, and distributes records. The processing engines receive records, calculate partition keys using a variable-length key pipeline hash unit to determine the target partition, and use a length-aware write merging unit to merge multiple records pointing to the same partition on-chip into cache line-aligned data blocks before writing them to the storage system. Therefore, this invention natively supports variable-length data, improving system throughput and versatility in a tightly coupled environment.

The application discloses a memory controller, a storage system, a device and a write merging method. The memory controller comprises a preparation module and a cache module; the preparation module is configured to send a first indication instruction to the cache module in the case that an address overlap condition is met between a first write address and a second write address; and the cache module is configured to merge the first write address and the second write address to obtain a third write address and merge first write data and second write data to obtain third write data in the case that the first indication instruction is received. From the perspective of write data correctness, the write merging mechanism is designed in the memory controller to merge write data, the data write correctness of the write request of address overlap is improved, the problem that the memory controller needs to be forced to suspend to ensure the data write correctness of the write request of address overlap is solved, and therefore the bandwidth utilization of the memory controller is improved.

The invention discloses a memory controller, a memory system, equipment and a write merging method. The memory controller comprises a preparation module and a cache module, the preparation module is configured to send a first indication instruction to the cache module under the condition that the first write address and the second write address meet an address overlapping condition; and the cache module is configured to combine the first write address and the second write address to obtain a third write address and combine the first write data and the second write data to obtain third write data under the condition of receiving the first indication instruction. From the perspective of write data correctness, the write merging mechanism is designed in the memory controller to merge the write data, so that the data write correctness of the write requests with the overlapped addresses is improved, and the problem that the memory controller needs to be forcibly suspended to ensure the data write correctness of the write requests with the overlapped addresses is solved; therefore, the bandwidth utilization rate of the memory controller is improved.

A processor 100 comprising a data buffer, the data buffer being configured as a write-combine buffer; and logic circuitry configured to receive from a further entity an input data stream for a write o

A processor includes a data buffer, the data buffer being configured as a write-combine buffer. The processor further includes logic circuitry which is configured to perform: receiving, from a further entity, an input data stream for a write operation, wherein the input data stream is received in blocks of data, and partitioning the data buffer into partitions, wherein the partitioning is based on a size of the blocks of data that are received. The logic circuitry is further configured to perform: writing each of the blocks of data to one of the partitions, each block of data being written to a partition of the data buffer based on an address associated with the respective block of data, and for each of the partitions, determining whether to initiate a draining of the respective partition to further memory based on the data that is stored in the respective partition.

The invention relates to the technical field of virtualization, in particular to a network data flow hardware unloading system and method for unified processing of heterogeneous descriptors. The system comprises a message pre-analysis module used for analyzing a Virtio data stream and outputting Virtio descriptor information and network message structure information; the descriptor normalization processing module is used for receiving the Virtio descriptor information and an SR-IOV descriptor of the SR-IOV data stream, and outputting descriptors in a unified format through normalization processing; the back-end hardware unloading module is used for receiving the descriptors with the uniform format and executing hardware unloading processing on the data packet; and the interruption / write-back merging module is used for performing completion state write-back and interruption reporting on the processed data packet. By arranging the descriptor normalization processing module, the Virtio heterogeneous descriptor and the SR-IOV heterogeneous descriptor can be accepted and processed at the same time, and unified processing of heterogeneous services on the hardware level is achieved.

The invention discloses a safe USB flash disk data processing method and system suitable for a power grid sensitive computing environment, and the method comprises the steps: firstly obtaining a drift spectrum, and coupling three parameters, namely, the parallelism degree, the aggregation degree and the window depth, into throughput gears; a throughput event, a failure event and a drift spectrum of a previous time slice are used as prior signals to perform adaptive throughput gear selection, and physical prior and online adaptation are combined, so that selection of throughput gears is adaptive to temperature and pressure drift and aging characteristics, stable throughput can still be maintained in an extreme environment or an aging scene, and the stability of the throughput is improved. And moreover, the steady-state throughput is greatly improved, the fluctuation is reduced, the time delay tail end is remarkably converged, and the safe USB flash disk has high parallelism and high reliability at the same time. Meanwhile, the random write of the host is merged into a super block before the authentication encryption is executed, so that the starting overhead and bus round-trip of the AEAD can be obviously reduced, the write amplification is reduced, the time delay is smoothed, and the pipeline utilization rate is closer to the bandwidth upper limit of the safe USB flash disk.

Write buffer circuit supporting store release combining of store operations from a memory access stage of a processor instruction pipeline for efficient processing of store release instructions, and related methods. The write buffer circuit is interfaced with an instruction pipeline of a processor to receive and commit (write data) executed store instructions to memory. The write buffer circuit allows launching of store release instructions from a store queue (STQ) to a write combining buffer (WCB) even if pending, older store instructions are not yet committed to non-cacheable memory. The write buffer circuit is configured to delay release of store release instructions from the WCB for their data to be written to non-cacheable memory until any pending, older store instructions have been committed. This facilitates combining of address related store-release instructions in the WCB that can be written to memory in a single write operation.

The application discloses a kind of safe U disc data processing method and system suitable for power grid sensitive computing environment, this method first obtains drift spectrum, and the three parameters of parallelism, aggregation and window depth are coupled as throughput gear, and the throughput event of last time slice, failure event and drift spectrum are used as prior signal to adaptively select throughput gear, by the combination of physical prior and online adaptation, not only make the selection of throughput gear and temperature and pressure drift and aging characteristics adapt, still can maintain stable throughput under extreme environment or aging scene, and greatly improve stable state throughput and reduce fluctuation, significantly converge long tail, realize that safe U disc has high parallelism and high reliability simultaneously.Meanwhile, the random write of host is merged into superblock before executing authentication encryption, can significantly dilute the start-up overhead and bus round trip of AEAD, reduce write amplification and smooth delay, so that pipeline utilization rate is closer to the bandwidth upper limit of safe U disc.

Write buffer circuit supporting store release combining of store operations from a memory access stage of a processor instruction pipeline for efficient processing of store release instructions, and related methods. The write buffer circuit is interfaced with an instruction pipeline of a processor to receive and commit (write data) executed store instructions to memory. The write buffer circuit allows launching of store release instructions from a store queue (STQ) to a write combining buffer (WCB) even if pending, older store instructions are not yet committed to non-cacheable memory. The write buffer circuit is configured to delay release of store release instructions from the WCB for their data to be written to non-cacheable memory until any pending, older store instructions have been committed. This facilitates combining of address related store-release instructions in the WCB that can be written to memory in a single write operation.

The application relates to an intelligent network card and a distributed object access method based on the intelligent network card. The intelligent network card comprises a read-write combination module and an adaptive prefetch module. The read-write combination module is used for combining read-write request times of access requests from a computing node to the same destination address in a time window, so as to reduce the read-write request times. The adaptive prefetch module is used for checking whether on-chip memory of the intelligent network card is hit when the computing node initiates an access request to a remote memory node, adding an entry in the read-write request into a pseudo-prefetch queue in a message buffer in the case of a miss, scoring a prefetch module corresponding to the read-write request according to an access cache hit rate, and adjusting an access priority based on the scores of the prefetch modules, so as to dynamically adjust a prefetch strategy. The application takes the intelligent network card as a different computing resource coordinator in a computing node, and uniformly accesses and prefetches on-chip resources to reduce redundancy.

Write buffer circuit supporting store release combining of store operations from a memory access stage of a processor instruction pipeline for efficient processing of store release instructions, and related methods. The write buffer circuit is interfaced with an instruction pipeline of a processor to receive and commit (write data) executed store instructions to memory. The write buffer circuit allows launching of store release instructions from a store queue (STQ) to a write combining buffer (WCB) even if pending, older store instructions are not yet committed to non-cacheable memory. The write buffer circuit is configured to delay release of store release instructions from the WCB for their data to be written to non-cacheable memory until any pending, older store instructions have been committed. This facilitates combining of address related store-release instructions in the WCB that can be written to memory in a single write operation.