A method of manufacturing a
semiconductor integrated circuit comprising a step of forming a lower-layer wiring, a step of forming a first viahole at a first
cross point at which the lower-layer wiring and an upper-layer wiring intersect with each other in a plurality of cross points of a viahole-formation
mask and forming a second viahole at a second
cross point at which the lower-layer and the upper-layer wirings do not intersect with each other in the plurality of cross points in a state in which a
metal wiring
mask corresponding to the lower-layer wiring, a
metal wiring
mask corresponding to the upper-layer wiring and the viahole-formation mask having the plurality of cross points are overlaid on one another, a step of forming a first via which is connected to the lower-layer wiring in the first viahole and forming a second via which is not connected to the lower-layer wiring in the second viahole, and a step of forming the upper-layer wiring in a state in which the upper-layer wiring is connected to the first via and covering the second via with an
insulation layer.