6 results about "Cascaded integrator–comb filter" patented technology

The application relates to a digital wave trap, a digital low-pass filter and a design method, a medium and an electronic device. The digital wave trap comprises a wave limit boundary anchoring unit and a wave limit zero point modulation unit which are cascaded in sequence, the wave limit boundary anchoring unit adopts a cascaded integral comb filter structure and is used for generating a first attenuation zero point at a boundary frequency of a target wave trap frequency band; the wave limit zero point modulation unit adopts a finite-length unit impulse response filter structure and is used for generating at least one second attenuation zero point in the target wave trap frequency band; and a continuous suppression band for the target wave trap frequency band is formed in the amplitude-frequency response of an output signal of the wave limit zero point modulation unit by the first attenuation zero point and the at least one second attenuation zero point. By using the digital wave trap provided by the application, a digital low-pass filter which can deeply and widely suppress power frequency interference and maintain strict linear phase and excellent low-pass characteristics can be designed without significantly increasing hardware resources and power consumption.

The invention discloses a synchronous phasor measurement method adopting CIC compensation filtering and a related device, and the method comprises the steps: carrying out the equal-time-interval sampling of an AC signal, obtaining a sampling sequence, carrying out the coordinate transformation of the sampling sequence, and constructing an original phasor through the coordinate transformation result; performing cascade integrator comb filtering on the original phasor to obtain a downsampled phasor result sequence; filtering the downsampling result phasor sequence by using a compensation filter to obtain a compensation filtering result sequence; and calculating the amplitude, phase angle, frequency and frequency change rate measurement value of the synchronous phasor according to the compensation filtering result sequence. The method and the related device can accurately measure the synchronous phasor, the frequency and the frequency change rate of the power system under the steady and dynamic conditions.

The invention belongs to the technical field of underwater communication, and particularly relates to a high-temperature metal underwater detection method and system based on an FPGA, and the method comprises the steps: capturing an underwater sound wave signal through an underwater sensor, and converting the underwater sound wave signal into an analog electric signal; amplifying the analog electric signal by using a variable gain amplifier; converting the amplified analog signal into a digital signal through an analog-to-digital converter; the frequency spectrum of the digital signal is shifted to a base band by adopting a digital orthogonal down-conversion technology so as to reduce the signal processing complexity; a cascaded integrator comb filter is used for filtering baseband signals, so that the consumption of hardware resources is reduced, and the operation rate is improved; underwater target detection of high-temperature metal is realized based on a CFAR threshold adjustable method, and a detection result is displayed through a graphical user interface. The method effectively overcomes noise interference in a complex underwater sound environment, improves the detection efficiency and adaptability, and is suitable for safety production scenes such as high-temperature metal underwater leakage detection.

This invention discloses a high-performance cascaded integrator-comb filter with two-stage compensation. The filter includes: an N-stage conventional cascaded integrator-comb (CIC) filter module, a first compensation filter, and a second compensation filter. The N-stage CIC filter module is used to perform signal decimation or interpolation and provide basic filtering characteristics; the first compensation filter is used to compensate for the passband attenuation of the CIC filter; and the second compensation filter is used to increase the stopband zero-suppression and attenuation of the CIC filter. This invention, by cascading two simple and parameter-adjustable compensation filters, improves the passband and stopband performance of the filter while maintaining low implementation complexity, making it particularly suitable for sampling rate conversion systems with high performance requirements.

The application relates to the technical field of filtering, and particularly provides a large-bandwidth multi-rate real-time signal processing method, system, device and storage medium, which comprises the following steps: acquiring a high-speed data stream output by an analog-to-digital converter (ADC); processing the high-speed data stream by using a dynamically configured multi-stage decimation filtering link, wherein the multi-stage decimation filtering link at least comprises a cascade integrated comb (CIC) filter, a half-band (HBF) filter and a coefficient-configurable finite impulse response (FIR) filter; in a signal processing process, the configuration state of the multi-stage decimation filtering link is dynamically switched in response to the change of a target signal bandwidth demand; the dynamic switching comprises changing the enabling states of the CIC filter and the HBF filter, and loading the FIR filter coefficients matched with the changed bandwidth; and the processed sampling data is cached. By using the dynamically configurable multi-stage decimation filtering link, adaptive processing of different bandwidth signals is realized.

The invention discloses a high-precision and low-delay analog-to-digital converter based on a proportional floating inverting amplifier, which solves the problems that in the prior art, the circuit power consumption overhead is relatively high, and linear scaling of power consumption along with sampling frequency is difficult to realize, and realizes that event driving can be supported and the power consumption is low. Comprising a first summator used for calculating a difference value between an input signal and an output signal of a feedback DAC module; the cascaded first-stage integrator, the cascaded second-stage integrator and the cascaded third-stage integrator are used for respectively carrying out integration processing on the difference signal and the upper-stage output signal subjected to gain coefficient scaling so as to realize noise shaping; the summing circuit is used for summing the input signal scaled by the feed-forward coefficient and the output signal of the three-stage integrator; the single-bit quantizer module quantizes the summation result to generate a digital code stream; the feedback DAC converts the digital code stream into an analog feedback signal; and the cascaded integrator comb filter filters the digital code stream and then outputs a Nyquist rate digital signal.