38 results about "Cascaded integrator–comb filter" patented technology

The invention discloses an all digital frequency converting method and a device thereof, being easily realized for hardware. The method and the device are essentially used for sample rate convertion of rational number-times of baseband signals and the convertion of the baseband signals and the intermediate frequency signals in digital communication. Under the coordination of control signals and enabling signals, the convertion of signal sample rate can be finished and the convertion of the baseband signals and the intermediate signals can be finished through the reasonable matching of variable integral number-times wave filtering and fraction-times interpolation. The system of the invention essentially comprises a frequency mixer, a cascade connection integral comb filter, a fraction-time interpolating device, a half-band filter, a signal shaping filter, a power detection module and a control interface. The configurable hardware implemented structure of the invention is applicable to a plurality of modulation methods, has the advantages of low resource consumption and good portability, and is used for various wireless communication systems such as multilevel phase shift keying (MPSK), orthogonal frequency division multiplex (OFDM), direct sequence spread spectrum (DSSS) and continuous phase modulation (CPM), etc.

A waveform compression and display technique saves both a peak detected version (background version) and a decimated / lowpass filtered version (foreground version) of a sampled electrical signal. The two versions are displayed simultaneously overlaid together in a contrasting manner so as not to obscure information contained in either of them. The lowpass filtered version uses a series of simple lowpass filters with decimation to produce a single data stream from a plurality of data streams derived from the sampled electrical signal. The single data stream may then be subjected to additional filtering, such as a cascaded integrator-comb filter, to obtain a desired frequency bandwidth. When displayed, the peak detect pixels adjacent the decimated / lowpass filtered pixels may be adjusted in intensity so that the low frequency information of the lowpass filtered waveform is not lost, while the peak detect pixels further from the lowpass filtered pixels are intensified to highlight the high frequency information. Alternatively the background version intensity may be controlled by a user control over a first range from zero to a predetermined maximum, and the foreground version may be controlled over a second range from a default intensity to a maximum, saturated intensity.

A non-integer decimation filter for decimating an input value includes a first integrator for integrating the input value in an input sample domain at an input sample rate and for generating a first integral of the input value at its output and a second integrator for integrating the first integral of the input value in the input sample domain at the input sample rate and for generating a second integral at its output. A calculation network is coupled to the outputs of the first and second integrators for combining the outputs of the first and second integrators with corresponding coefficients to generate intermediate output values in an output sample domain. A differentiator is configured to receive the intermediate output values from the calculation network and to generate a decimated output value at an output sample rate in which the output sample rate has a non-integer factor with respect to the input sample rate.

System and method for analyzing an input signal acquired from a physical system with a rotating element. A tachometer signal is received comprising rotation speed information for the rotating element. A time sequence is determined using the tachometer signal, comprising time values for the rotating element at substantially equal angle increments, e.g., by edge detection software or timer / counter. A software-based first digital interpolation filter, e.g., a Cascade-Integrator-Comb filter, is applied to the time sequence, generating a modified time sequence. A digitized data signal is received comprising data for the rotating element at substantially equal time increments. A second software-based digital interpolation filter is applied to the data signal, generating a modified data signal which is re-sampled using the modified time sequence to generate an angle domain data signal, comprising data signal values at substantially equal angle increments, where the angle domain data signal is usable to analyze the physical system.

A non-integer CIC interpolation filter is provided for use in sigma-delta digital-to-analog systems, which realizes non-integer interpolation but eliminates the need for coupling of the integrators in the output domain. The present non-integer interpolation filter provides for more attenuation to all of the aliases of the input signal and has eliminated the need of complex computations.

This invention discloses a method for realizing bandpass filtration utilizing two cascade integral comb filters of different cut-off frequencies, which takes signals necessary for bandpass filtration as two paths of input signals to carry out low pass filtration and adjustment to time delay and gain of them then to cancel the processed signals. This invention also discloses a device for realizing bandpass filtration by two cascade integral comb filters.

The invention relates and discloses an interpolating digital filter device which is applied to a wireless medium range sensor network physical layer, comprising an interpolating digital filter module based on FIR (Finite impulse response filter) and an interpolating digital filter module based on CIC (Cascaded integrator-comb filter). The interpolating digital filter module based on FIR comprises a shift register time delay module, a multiplication module, a coefficient selector module, and an accumulator module. Wherein, the accumulator module comprises a register module and an adder module. The interpolating digital filter module based on CIC comprises a pectinate unit module, an interpolating unit module and an integral unit module. The invention is characterized in occupying less hardware resource, being applied to higher system clock rate, smaller passband ripple, more stopband attenuation and so on. The invention is applicable to a broadband wireless transceiver, in particular to a wireless broadband transmission system based on OFDM (Orthogonal Frequency Division Multiplexing) in the mobile environment.

The present invention may relate generally to a circuit for converting a first digital signal having a first sample rate to second digital signal having a second sample rate. The circuit may comprise a cascaded integration-comb filter and a fractional sample rate converter. The fractional sample rate converter may be configured to perform fractional sample rate conversion. A first of the cascaded integrator-comb filter and the fractional sample rate converter may be configured to receive the first signal having the first sample rate and to generate a third digital signal having a third sample rate different from the first and second sample rates. A second of the cascaded integrator-comb filter and the fractional sample rate converter may be configured to receive the third signal having the third sample rate and to generate the second signal having the second sample rate.

The invention relates to the communication field and particularly discloses a filtering device and a filtering method of a cascaded integral comb filter. In the invention, by the multiplexing of a cascaded integrator and a cascaded comb filter contained in a cascaded integral comb filter, the same cascaded integral comb filter can work as a cascaded integral comb extraction filter or as a cascaded integral comb interpolation filter so as to avoid arranging a cascaded integral comb filter in a receiving channel or a sending channel and favorably save logic resources and decrease the cost while reaching performance indexes.

The invention relates to an ultrasonic imaging post-processing method and a device of the ultrasonic imaging post-processing method. The ultrasonic imaging post-processing method is used for processing output signals of the front end of the ultrasonic imaging beam forming and comprises the following steps: (1) conducting mixing processing to the output signals of the front end of the ultrasonic imaging and an orthogonality I component and an orthogonality component Q are acquired, (2) conducting lowpass filtering processing to two line orthogonal signals through a cascading integral comb filter and meanwhile conducting down-sampling in the middle of cascading integral comb filter. The ultrasonic imaging post-processing method further comprises steps of revising a transitional zone of frequency response of the cascading integral comb filter through a correcting filter. The step (2) further comprises the following steps:(1) sending the orthogonality I component and the orthogonality Q component after the mixing processing into the cascading integral comb filter and an output signal Ii (n) and an output signal Qi (n) are acquired, (2) conducting down-sampling to the signal Ii (n) and the output signal Qi (n) according to post-processing requirements to the signal Iid (n) and the output signal Qid (n), (3) processing Iid (n) and Qid (n) through the cascading integral comb filter and an output signal Iiedc (n) and an output signal Qidc (n) of the cascading integral comb filter are acquired.

The invention provides a cascade integrator comb filter and an implementation method thereof. The cascade integrator comb filter if of a composite structure comprising an FIR (Finite Impulse Response) structure and an IIR (Infinite Impulse Response) structure which are connected in series with each other, and comprises a first sub-cascade integrator comb filter of the FIR structure at the front end, and a second sub-cascade integrator comb filter which is located at the rear end, connected in series with the first sub-cascade integrator comb filter and is of an IIR structure. Compared with the prior art, the cascade integrator comb filter is capable of overcoming the defects of the existing single structure (FIR structure or IIR structure) with the advantages thereof, thereby achieving high speed through the change of area; and balance is realized between realization cost and power consumption; and therefore, the optimal performance cost is obtained.

A cascaded integrator comb filter includes a first integrator that receives an input signal x[n] and provides an integrated signal, and a fractional integrator that also receives the input signal x[n] and provides a fractional integrated signal. A summer sums the integrated signal and the fractional integrated signal and provides a summed signal indicative thereof to a second integrator, which receives and integrates the summed signal to provide a second integrator output signal. A decimator unit receives the second integrator output signal and provides a decimated signal to a differentiator that receives the decimated signal and provides a differentiated signal.

The invention discloses an oversampling type Pipeline SAR-ADC system. The system comprises an oversampling switch, an analog to digital conversion system and a digital expansion system which are orderly connected with each other, wherein the analog to digital conversion system comprises successive approximation type analog to digital conversion modules and a register; the number of the successiveapproximation type analog to digital conversion modules is N, and N is a positive integer greater than or equal to 2; and N successive approximation type analog to digital conversion modules are orderly connected to form N orders, and the order of each successive approximation type analog to digital conversion module is corresponding to the sequence of input signals in all successive approximationtype analog to digital conversion modules, and a digital output end of each successive approximation type analog to digital conversion module is connected with an input end of the register. The digital expansion system comprises a digital bit add module and a clock control module; and the digital bit add module comprises a cascade integrator comb filter and a moving average filter connected withthe cascade integrator comb filter. The oversampling type Pipeline SAR-ADC system provided by the invention uses fewer components, is easy to realize and low in cost, and can improve the output rate and resolution when being applied.

The invention provides a digital decimation filter. The digital decimation filter comprises a cascade integral comb filter, a cascaded Lagrange half-band filter and an FIR filter, which are orderly connected. The digital decimation filter has the advantages of less pass band dropping, small quantized noise power after filtering, and less power consumption.

The invention relates to a cascade integral comb filter, which uses shift register to overcome the defects of traditional cascade integral comb filter which only can transform the data speed of one channel, to need distributing cascade integral comb filter for each channel when transforming the data speed of several channels, to cause over-large area in FPGA or ASIC. With affecting property, the invention can transform the data speed of several channels with only one cascade integral comb filter, to reduce the realize area of FPGA or ASIC, and save cost.

A non-coherent frequency shift keying transmitter for up-converting a baseband signal to a radio frequency signal is provided. The non-coherent frequency shift keying transmitter applies the interpolation method in a digital frequency synthesizer to replace the conventional Phase Locked Loop (PLL) circuit. The micro processing unit receives a baseband signal firstly, then the baseband signal is converted to a RF signal via a digital synthesizer, a numerical controlled oscillator, a cascaded integrator-comb filter, and a digital-analog converter. The RF signal is then transmitted via a local oscillator, a band-pass filter, a power amplifier, and a transmitting end. This circuit eliminates unnecessary analog devices so that fabrication migration issue is avoided. Further, the modulated RF signal is more stable than that of the conventional modulator, and has a more efficient spectrum control and a better performance on the receiver end. A non-coherent FSK transmitting system is also provided in the present invention.

The invention discloses a filter with a three-stage cascade structure, which adopts a three-stage cascade structure of a cascade integrator comb (CIC) filter, a cosine cascade filter, a linear interpolation second-order polynomial (ISOP) and a half-band filter, and improves the CIC filter, the cosine cascade filter and the half-band filter, and therefore, the area and the power consumption of the whole hardware are reduced, the performance of the digital filter is greatly improved, and the purpose of improving the output precision is achieved.

This invention relates to a cascade integral comb filter, comprising integral module, extract module and comb module, and place inside data port and synchronous signal port; the said synchronous signal port is used for transmitting synchronous signals; the said data port is used for the data input according to synchronous signals, and control the transmitted data through the synchronous signals. Through this invention, can adopt data synchronous signal to control data input, solve the problem that the frequency of input data is restricted result from frequency of data transmitted must be the same with master clock in existing technologies, but the invention easy to implement serial processing, and can reduce the time delay in procession. In addition, the invention can also dynamically control variable sample rate and or variable sample phase through the variable counter and comparator set in extract module, thus facilitate the expansion of filter. And the invention can also dynamically control variable exponent number through the selector set in the integral module or comb module.

The invention discloses a signal demodulation processing plate for a satellite communication gateway station, including an intermediate frequency signal receiver. The intermediate frequency signal receiver is connected with at least two A / D converters, one A / D converter is directly connected with an FPGA unit, and the rest A / D converters are all connected with a DDC. The DDC is connected with the FPGA unit. The FPGA unit is connected with a DSP unit and a communication interface. The FPGA unit comprises a numerical control oscillation module. The numerical control oscillation module is connected with a cascaded integrator comb filter module. The cascaded integrator comb filter module is connected with a halfband filter module. The halfband filter module is connected with a channelization poly-phase filterbank module. The signal demodulation processing plate for the satellite communication gateway station utilizes the FPGA to achieve the DDC function, and the FPGA unit is internally provided with a channelization poly-phase filterbank, thereby achieving multi-channel signal simultaneous processing on the basis of not increasing the processing plate structure.

This invention relates to a cascade integral comb filter, comprising integral module, extract module and comb module, and place inside data port and synchronous signal port; the said synchronous signal port is used for transmitting synchronous signals; the said data port is used for the data input according to synchronous signals, and control the transmitted data through the synchronous signals. Through this invention, can adopt data synchronous signal to control data input, solve the problem that the frequency of input data is restricted result from frequency of data transmitted must be the same with master clock in existing technologies, but the invention easy to implement serial processing, and can reduce the time delay in procession. In addition, the invention can also dynamically control variable sample rate and or variable sample phase through the variable counter and comparator set in extract module, thus facilitate the expansion of filter. And the invention can also dynamically control variable exponent number through the selector set in the integral module or comb module.

The present invention provides a front end device based on DVB digital TV RF channel measurement, which comprises one or more FEC units, one or more interpolation filter units, one or more digital QAM units and one or more digital control oscillators. The invention uses interpolation filter composed by multiphase digital filter, null filter, and cascade integration comb filter, integrates digital filter without complex multiple and adding framework, simplifies greatly interpolation scheme for digital communication, and decreases realization cost.

The invention relates to a cascade integral comb filter, which uses shift register to overcome the defects of traditional cascade integral comb filter which only can transform the data speed of one channel, to need distributing cascade integral comb filter for each channel when transforming the data speed of several channels, to cause over-large area in FPGA or ASIC. With affecting property, the invention can transform the data speed of several channels with only one cascade integral comb filter, to reduce the realize area of FPGA or ASIC, and save cost.

A flyback converter is described that in some examples includes an integrated circuit that includes a delta-sigma converter and a cascaded integrator-comb filter configured to determine: a proportional factor, an integral factor, and a derivative factor associated with a secondary-side voltage across a secondary-side winding of the converter. The integrated circuit uses each factor to control a secondary switching element to perform synchronous rectification. In some examples, the flyback converter includes an auxiliary winding at the primary side of the transformer and a knee point voltage detection unit. The knee point voltage detection unit is configured to determine, based on an analog input indicative of a voltage at the auxiliary winding, an integral of value and detect, based on the integral value, a knee point voltage associated with the voltage at the auxiliary winding. A controller may use the detected knee point to control a primary side switch.