47 results about "CPU core voltage" patented technology

A CPU core voltage switching circuit installed in a personal digital assistant wherein, when the personal digital assistant is using an application software product, a CPU clock frequency is reduced to a half of the frequency used when the personal digital assistant is in an initial start state or a memory data initialization state.

A selectable control over multiple clock frequency / voltage level combinations that can be activated in a processor. A table can be placed in hardware that defines multiple combinations of CPU clock frequency and CPU operating voltage. By placing the table in hardware, it can be assured that all the various combinations will work for the particular processor device. Software can then be used to select a combination from this table, to control the actual frequency / voltage combination that is being implemented at a given time. This allows dynamic control over the power / performance tradeoff, so that the system can see maximum power savings consistent with acceptable performance, as operating and environmental considerations continue to change the most desirable selections.

A method for CPU power management and bus optimization. First, the bus operates at an initial bus bandwidth and an initial bus frequency first. Next, power management settings of the CPU, the Northbridge and the Southbridge are initialized, such that the CPU operates at a CPU operating frequency with a CPU operating voltage. Next, a CPU operating frequency and voltage adjustment is output to the Southbridge. Next, a bus disconnection signal is output by the Southbridge to disconnect the CPU and the Northbridge, and a timer for calculating an elapsed time value is initialized. Next, the CPU operating frequency and the CPU operating voltage are adjusted according to the CPU operating frequency and voltage adjustment. Next, a bus connection signal is output by the Southbridge when the elapsed time value reaches a predetermined value. Next, the CPU and the Northbridge are reconnected by the bus according to the bus connection signal. Finally, the bus operates at the bus operating bandwidth and the bus operating frequency, and the CPU operates at the adjusted CPU operating frequency with the adjusted CPU operating voltage according to the CPU operating frequency and voltage adjustment.

Disclosed is a driving voltage controller of sense amplifiers for a memory device which prevents the sense amplifier from being over-driven when an external power voltage is used for an internal driving voltage of the sense amplifier. Reference voltage generator generates a reference voltage. Core voltage generator generates a core voltage to be used for driving voltage of sense amplifier. Comparator compares the core voltage generated by core voltage generator with the reference voltage generated by reference voltage generator. Clamp adjusts a level of the core voltage generated by the core voltage generator based on an output signal of comparator. In the case where an external power used for a driving voltage of the sense amplifier is excessively high, the comparator compares the external power voltage with the reference voltage. When the driving voltage of sense amplifier exceeds the reference voltage, the clamp drops the driving voltage of sense amplifier. Thus, the core voltage can be stably supplied.

An apparatus and method for measuring output current and power in real-time is provided for a CPU core powered by a DC-to-DC power converter having active voltage positioning. In an embodiment of the invention, a switched mode power converter comprises at least one power switch operatively coupled to an input voltage source, an output filter operatively coupled to the at least one power switch to provide an output voltage and output current to a load, and a control circuit coupled to the at least one power switch. The control circuit activates the power switch with a duty cycle controlled to regulate at least one of the output voltage and the output current. The control circuit receives a first control signal defining a desired value for the output voltage, a second control signal defining a relationship between voltage input and current draw for the load, and a voltage sense signal corresponding to an actual value of the output voltage. The control circuit thereby provides a measurement of load current.

A reinforcing bar binding machine is provided with a device for detecting a power supply voltage during a binding wire twisting step subjected to the heaviest load and comparing the power supply voltage with a predetermined CPU operation voltage, and a control device for driving a motor in a reverse direction when the voltage has dropped below the predetermined CPU operation voltage. The power supply voltage during operation is monitored, and twisting operation is suspended before the voltage drops below the CPU operation voltage, whereby the binding wire twisting mechanism is returned to the initial position. Therefore, it is possible to prevent the binding wire twisting mechanism from being stopped while grasping the binding wire, when the CPU stops.

The invention discloses a low voltage differential signal driver adaptive to various IO power supplies. The low voltage differential signal driver comprises a differential conversion module, a pre-amplifier and a driving amplification circuit, wherein the differential conversion module is used for converting a low-voltage digital signal of a core into a differential voltage signal; the pre-amplifier is used for amplifying the differential voltage signal and outputting a positive path of voltage signals and a negative path of voltage signals; and the driving amplification circuit is used for amplifying the positive and negative paths of output signals of the pre-amplifier to obtain the output of the driver. The low-voltage differential signal driver automatically changes through bias along with the power supply and changes the control range of operational amplification to form a new circuit device. The low voltage differential signal driver is adapted to a microelectronic circuit of which core voltage is changed from low voltage 0.9 V to 1.5 V and IO voltage is changed from 1.8 V to high voltage 5 V through a topological structure where a low voltage core circuit and a high voltage IO circuit are separated and the bias which comes from the low voltage of the core and is flexibly adapted to the high voltage of the IO power supply, can be used for a multi-path LVDS driver and can transmit data at a rate of 1 G bit per second (bps).

A voltage regulator module (VRM) and a voltage regulating system for a CPU. The VRM supplies a supply core voltage corresponding to a VID signal output from the CPU. A core voltage generator generates the core voltage and a voltage regulation control unit controls the core voltage based on a spec signal which decides a percent voltage regulation of the core voltage, the core voltage having the percent voltage regulation corresponding to the spec signal, which is output by the CPU. The VRM and the voltage regulating system according to the present invention supply a stable core voltage that the CPU requires, regardless of a class of the CPU, by receiving information on the voltage the CPU requires from the CPU.

A digital circuit implementing pulse width modulation controls power delivered in what one can model as a second order or higher order system. An exemplary control plant could embody a step-down switch mode power supply providing a precise sequence of voltages or currents to any of a variety of loads such as the core voltage of a semiconductor unique compared to its input / output ring voltage. One of several algorithms produce a specific predetermined sequence of pulses of varying width such that the voltage maintains maximally flat characteristics while the current delivered to the load from the system plant varies within a range bounded only by inductive element continuous conduction at the low power extreme and non-saturation of the inductor core at the high power extreme. The specific pulse width modulation sequence controls a plant such that the voltage maintains maximally flat characteristics in one embodiment without a feed-forward or feedback loop physically embodied in the control system thereby reducing the parts cost or control semiconductor production yield cost while enhancing noise immunity and long term reliability of the control system. Several specific algorithms maintain maximally flat voltage despite extreme load variations therewith control plant element parameters otherwise exacerbating excessive voltage fluctuation during the given current transients.

Systems and methods are disclosed that may be employed to calibrate current sense circuitry of CPU core voltage (Vcore) DC / DC voltage regulation circuitry by coupling an individual Vcore phase of a VR as a current source to a VSA phase of the same VR so that the Vcore phase acts as a current sink for the coupled Vcore phase during calibration of the current sense circuitry of the individual Vcore phase.

A reinforcing bar binding machine is provided with a device for detecting a power supply voltage during a binding wire twisting step subjected to the heaviest load and comparing the power supply voltage with a predetermined CPU operation voltage, and a control device for driving a motor in a reverse direction when the voltage has dropped below the predetermined CPU operation voltage. The power supply voltage during operation is monitored, and twisting operation is suspended before the voltage drops below the CPU operation voltage, whereby the binding wire twisting mechanism is returned to the initial position. Therefore, it is possible to prevent the binding wire twisting mechanism from being stopped while grasping the binding wire, when the CPU stops.

A CPU core voltage supply circuit includes a reference voltage generator, a differential operation amplifier, a power element, a feedback circuit and a first capacitor. The reference voltage generator outputs a first reference voltage. The differential operation amplifier has a positive input end, a negative input end and an output end. The positive input end is connected to the reference voltage generator for receiving the first reference voltage. The power element has a receiving terminal and a current output terminal. The receiving terminal is connected to the output end of the differential operation amplifier. The feedback circuit is connected to the current output terminal and outputs a feedback voltage to the negative input end of the differential operation amplifier. The first capacitor has an end connected to the current output terminal of the power element and the other end receiving a first voltage, thereby providing a CPU core voltage.

A semiconductor memory device reduces power consumption with maintaining quality of an internal power voltage and a core voltage. The semiconductor memory device reduces power consumption with sufficiently maintaining a core voltage during precharge. The semiconductor memory device includes a command decoder receiving external control signals to output an active signal and a precharge signal, an internal power voltage generation controlling unit receiving the active signal and the precharge signal for activating an internal power voltage active signal for a predetermined time, a core voltage generation controlling unit receiving the active signal, the precharge signal and the internal power voltage active signal for activating a core voltage active signal for a predetermined time, an internal power voltage generating unit for generating an internal power voltage during the activation period of the internal power voltage active signal; and a core voltage generating unit for generating a core voltage during the activation period of the core voltage active signal.

The invention discloses a system power consumption regulating circuit, a system power consumption regulating method and electronic equipment. The circuit comprises a system current detection circuit, a power supply management circuit and a CPU (Central Processing Unit) core voltage regulating circuit, wherein the system current detection circuit is used for detecting current in a system and outputting a detected current magnitude signal to the CPU core voltage regulating circuit; the CPU core voltage regulating circuit is used for receiving the current magnitude signal transmitted by the system current detection circuit and feeding back a core voltage regulating signal to the power supply management circuit according to the current magnitude signal; the power supply management circuit is used for regulating core voltage which is output to a system CPU according to the core voltage regulating signal to regulate the power consumption of the system. By adopting the technical scheme provided by the invention, when the system works, the magnitude of the current in the system is detected and the core voltage output to the CPU is regulated according to the magnitude of the current, so as to achieve the goals of regulating the power consumption of the system, reducing the situations that system emits heat and components are heavily overloaded with work and prolonging the service life of the system.

The invention discloses a core voltage control device, which is suitable for a central processing unit. The core voltage control device comprises a level conversion unit, a time delay unit and a logical unit, wherein the input end of the level conversion unit receives a first voltage signal and is used for level conversion of the first voltage signal, and the output end of the level conversion unit generates a second voltage signal, wherein the first voltage signal indicates the stable electrifying state, and the second voltage signal indicates the size of the core voltage; the time delay unit performs time delay the second voltage signal, so as to generate a third voltage signal; and the logical unit is coupled to the time delay unit, and used for performing logic operation on the third voltage signal and a fourth voltage signal which is transmitted by a power supply and generating a fifth voltage signal to control whether a core voltage generator supplies the core voltage to the central processing unit or not, wherein the fourth voltage signal indicates the power state.

A CPU core voltage supply circuit includes a reference voltage generator, a differential operation amplifier, a power element, a feedback circuit and a first capacitor. The reference voltage generator outputs a first reference voltage. The differential operation amplifier has a positive input end, a negative input end and an output end. The positive input end is connected to the reference voltage generator for receiving the first reference voltage. The power element has a receiving terminal and a current output terminal. The receiving terminal is connected to the output end of the differential operation amplifier. The feedback circuit is connected to the current output terminal and outputs a feedback voltage to the negative input end of the differential operation amplifier. The first capacitor has an end connected to the current output terminal of the power element and the other end receiving a first voltage, thereby providing a CPU core voltage.

The invention provides a device and a method for dynamic regulation of core voltage of an embedded processor. The device comprises a business statistical analysis module, a core voltage selection module, an input and output control module and a core voltage adjuster. The business statistical analysis module, the core voltage selection module and the input and output control module are positioned in the embedded processor and are connected in sequence, the input and output control module is connected with the core voltage adjuster. The method includes the following steps: acquiring and counting current business data of the embedded processor for determining load data; determining a core voltage value according to the load data; determining an input and output control signal according to the core voltage value; changing a feedback divider resistance combination of the core voltage adjuster by the input and output control signal, and then changing the size of the output voltage of the core voltage adjuster; and providing the output voltage to the embedded processor by the core voltage adjuster. By the aid of the device and the method for dynamic regulation of the core voltage of the embedded processor, the real-time and dynamic adjustment of the core voltage of the embedded processor is achieved, and use efficiency of power consumption of the embedded processor is effectively improved.

Disclosed is a driving voltage controller of sense amplifiers for a memory device which prevents the sense amplifier from being over-driven when an external power voltage is used for an internal driving voltage of the sense amplifier. Reference voltage generator generates a reference voltage. Core voltage generator generates a core voltage to be used for driving voltage of sense amplifier. Comparator compares the core voltage generated by core voltage generator with the reference voltage generated by reference voltage generator. Clamp adjusts a level of the core voltage generated by the core voltage generator based on an output signal of comparator. In the case where an external power used for a driving voltage of the sense amplifier is excessively high, the comparator compares the external power voltage with the reference voltage. When the driving voltage of sense amplifier exceeds the reference voltage, the clamp drops the driving voltage of sense amplifier. Thus, the core voltage can be stably supplied.

A power supply circuit for a sense amplifier of a semiconductor memory device is disclosed. The power supply circuit includes a control signal generator for generating a control signal which is activated upon a write operation, a multiplexer for selecting and outputting one of a first reference voltage and a second reference voltage input to the multiplexer, in response to the control signal, and a core voltage source for generating a core voltage in response to an output voltage from the multiplexer.

The invention discloses a computer power outage and power failure protective system. The system comprises a power supply enabled circuit and a mainboard CPU core voltage acquisition program, and the power supply enabled circuit comprises a power supply storage circuit, a voltage stabilizing circuit, a voltage boosting circuit and a computer power voltage detection judging circuit; the computer mainboard power failure protective system detects that a computer is suddenly in outage and conducts power-off, and a detection circuit detects the change of the computer voltage; when the voltage value reaches a certain threshold value, the power supply enabled circuit of an emergency power supply is switched, voltage stabilization of the power supply is conducted, and a computer program acquires core voltage data of a mainboard CPU in real time; when the data reaches a preset threshold value, the system controls the computer automatically and conducts power-off, and the protective effect for computer mainboard hardware is achieved.

A CPU voltage testing system and method uses a parameter storing unit to store a number of VID codes and a plurality of allowable voltage ranges. A number of VID code control signals corresponding to the number of the VID codes are sent to a VID code coding unit to control a voltage converting module to output corresponding voltage signals to a CPU. A voltage collecting unit collects CPU core voltages of the CPU and outputs the collected CPU core voltages to a data processing unit. The data processing unit can determine whether the collected CPU core voltages are within the plurality of allowable voltage ranges via comparing with a number of testing parameters stored in the parameter storing unit.

A CPU core voltage switching circuit installed in a personal digital assistant wherein, when the personal digital assistant is using an application software product, a CPU clock frequency is reduced to a half of the frequency used when the personal digital assistant is in an initial start state or a memory data initialization state.

The disclosure provides a voltage testing device and a method. A voltage testing device includes a PCB, a digital switch, and a detecting chip. The PCB includes a CPU socket, a signal producing chip, and a voltage regulator connected to the CPU socket. The digital switch sets predetermined data. The detecting chip is inserted in the CPU socket. The detecting chip includes a reading module, a converting module, a sending module, and a control module. The signal producing chip sends a start-up signal to the control module. The converting module coverts the predetermined data to SVID data. The sending module sends the SVID data to the voltage regulator. The voltage regulator sends a CPU voltage to the CPU socket. The voltage value testing device calculates a value of the CPU voltage to determined if the value of the CPU voltage associates with a voltage corresponding to the predetermined data.

The invention discloses a CPU working voltage control system, which comprises a power supply device, a power supply control chip and a system controller, wherein the power supply device is used for providing working power for a computer; the power supply control chip is used for converting a voltage provided by the power supply device into the working voltage of the CPU and outputting the working voltage; and the system controller is used for controlling the operation of the power supply control chip and performs information communication with the CPU to acquire the next working voltage of the CPU; and the system controller sends a control signal in advance to the power supply control chip on the basis of the current voltage output according to the next working voltage of the CPU, so that the power supply control chip can regulate the output voltage to the next working voltage of the CPU in advance according to the control signal. The invention also relates to a CPU working voltage control method.

A core voltage discharge driver prevents a core voltage discharging operation from interrupting the core voltage generating operation. The core voltage discharge driver includes a comparing unit configured to compare a core voltage generating control signal for controlling generation of a core voltage with a core voltage discharging control signal for controlling discharge of the core voltage, and an adjusting unit configured to adjust the core voltage discharging control signal based on a comparison result of the comparing unit.

The invention relates to a device for generating driving voltage for sense amplifier, which has the boost ability of generating the core voltage for the sense amplifier. The invention comprises: a voltage output device which is used to output the predetermined voltage value to drive the sense amplifier to a pitch point; a pressure-boosting device for the first core voltage which is connected between the power supply and the pitch point; and a pressure-boosting device for the second core voltage which is connected between the power supply and the pitch point, wherein, the first and the second core voltage pressure-boosting devices are orderly conducted to increase the voltage level of the pitch point connected with the sense amplifier to the power supply voltage level. The device for generating driving voltage for sense amplifier has the advantages that the of enhancing the effectiveness of the sense amplifier, executing the detection amplification in a short time, enhancing the core voltage used as driving voltage since the first and the second core voltage pressure-boosting devices are orderly conducted, reducing the power noise, and reducing power consumption since each core voltage pressure-boosting driver can also be configured in each memory bank.

An apparatus for testing working voltage of a central processing unit (CPU) includes a programmable logic device (PLD) having a dummy load, a voltage regulating controller, a CPU socket and a south bridge. The CPU socket is electrically connected to the voltage regulating controller via a series voltage identification (SVID) bus. The south bridge outputs a CPU voltage determining signal. The dummy load is electrically connected to the voltage regulating controller via the SVID bus. The PLD receives the CPU voltage determining signal, and outputs a voltage requesting signal via the SVID bus. The voltage regulating controller receives the voltage requesting signal, and outputs a CPU working voltage to the CPU socket accordingly. The PLD detects the CPU working voltage on the CPU socket, and determines whether the CPU working voltage meets requirements of specification.