34results about How to "Improve addressing speed" patented technology

A gate driving circuit drives a plurality of gate lines arranged in a display panel. The gate driving circuit includes a shift register having at least two stages of shift register units, and a gate enable circuit. Each shift register unit includes a gate signal output terminal configured to output a gate signal. The gate enable circuit includes a plurality of gate enable units. Each gate enable unit corresponds to one of the shift register units and includes an input terminal connected to the gate signal output terminal of the corresponding shift register unit, an output terminal connected to a corresponding one of the gate lines, and an enable signal input terminal configured to receive an enable signal. Each gate enable unit is configured to selectively output the gate signal of the corresponding shift register unit to the corresponding gate line based on the state of the received enable signal.

The invention discloses an addressing system and method aimed at layering host marking and based on overlaying DHT; structure of each addressing server in the system is identical and is provided with a node accessing and exiting processing module, an information maintenance module, a route searching module, a mapping record information memory module, and an overlaying DHT structure establishing and maintenance module. The addressing method is to set up the overlaying DHT first: non-semantic host identifiers used in the network are hierarchically transformed; area marks indicating the locating area position of each node are added; then each node is divided into different areas, and each area DHT is set up respectively; finally, all the area DHT are overlaid together to constitute a global DHT; when routes are looked for and transmitted, a next hop is chosen in priority in the area DHT based on the overlaying DHT; trans-regional routing times should be reduced to the fully extent to improve routing efficiency; each operation of registration/updating is carried out in two DHT simultaneously to realize equity of load on balance and economy.

An organic light emitting diode display and a method for driving the same are disclosed. The organic light emitting diode display includes a display panel including a plurality of pixels, a display panel driver configured to drive signal lines of the display panel, and a timing controller configured to divide one frame into a plurality of subframes, divide data of an input image at each bit, map the data of the input image to the plurality of subframes, control an operation of the display panel driver, and adjust data addressing speeds of the plurality of subframes for adjusting the emission times of the upper and lower display lines of the display panel differently.

An address generator for use in conjunction with a fast Fourier transform processor includes an efficient architecture for computing the memory addresses of input data points, output data points and twiddle coefficients. In particular, multiplication operation in the calculation of memory addresses is minimized. Instead, a cascaded series of adders is used, in which the output of one adder is input to the next adder. At each stage of the cascaded adders, the same input variable is successively added. The cascaded adder structure is used in the writing address generator, the reading address generator and the twiddle coefficient address generator. In addition, a plurality of modulo N circuits is used in series with the cascaded series of adders to generate the twiddle coefficient addresses.

A plasma display panel includes a magnesium oxide film (18) that covers electrodes (X, Y) and is exposed to a discharge gas space (31). The magnesium oxide film (18) includes silicon and calcium as impurities, and the content of the impurities in the magnesium oxide film (18) is 800 to 2050 ppm by weight. By suppressing the total content of silicon and calcium in the film to 800 to 2050 ppm by weight, the discharge start voltage can be reduced by no less than 20 volts.

Increase of an address voltage change amount of a PDP is suppressed. X and Y electrodes which are a display electrode pair arranged on a plate; a dielectric layer covering the X and Y electrodes; and a protective layer covering the dielectric layer are provided. The protective layer includes an MgO film deposited on a surface of the dielectric layer and a plurality of MgO crystalline particles attached on the MgO film. Also, by using (110) orientation as a crystal orientation of the MgO film, a crystal density of the MgO film can be increased, so that an increase of the address voltage change amount can be suppressed.

The invention discloses an internal storage for a computer. The internal storage comprises a plurality of first storage bodies, a second storage body, a first addressing unit, a second addressing unit, a write-in unit, a read-out unit, a clock unit and a control unit. The first storage bodies comprise a plurality of basic storing units, the basic storing units are arranged in a three-dimensional array mode, and a shifting register is arranged between every two adjacent first storage bodies. The second storage body comprises a plurality of basic storing units arranged in a one-dimensional linear mode, and a bi-direction transmission door is arranged between the second storage body and each first storage body and internally provided with a lock device. The first addressing unit comprises an address pointer with four dimensions. The second addressing unit comprises an address pointer with one dimension. The write-in unit is connected with the second storage body. The read-out unit is connected with the second storage body. According to the internal storage for the computer, the defects in the prior art can be overcome, and the addressing, reading and writing speed is improved by improving a data storage structure.

The invention relates to a drive method of an electrode of a groove type plasma metal screen plate during initializing period; when a groove type plasma scanning electrode comes into the initializing period, a drive circuit exerts a voltage controlled waveform on the electrode of the metal screen plate so as to guarantee that the electrode of the metal screen plate does not produce a weak discharging process against the scanning electrode and an addressing electrode during the weak discharging process produced between the scanning electrode and the addressing electrode in a first half of the initializing period; and in the first part and the rear part of the initializing period, the constant voltage controlled waveform exerted by the drive circuit on electrode of the metal screen plate is utilized to lead the scanning electrode and the electrode of the metal screen plate to generate the weak discharge; a positive wall charge on the surface of a dielectric layer on the addressing electrode is kept unchanged so as to guarantee that the positive wall charge accumulated on the surface of the dielectric layer on the addressing electrode approximates to the positive wall charge starting up a voltage level, thereby being helpful to improve the addressing speed, reduce the luminance of back side, improve the consistency of the addressing of the entire screen, reduce the occurrence of a wrong discharging and increase the contrast ratio of a SMPDP greatly.

The invention discloses a resolution image processing system based on embedded type. The resolution image processing system based on embedded type comprises a camera interface of Camera Link, SSRAM with capacity of 4M*16 bit, RPGA1EP3C80F780I7, SDR SDRAM, EP3C80F780I7 and a display drive; two SDR SDRAMs of 16M*16 bit are used for displaying the cache transmitted by the kilomega network; FPGA2 used for performing the tasks except for panorama unrolling and bell interpolation operation, including the drive for display, receiving and sending of the gigabit Ethernet; a gigabit Ethernet interface, a display interface used for displaying the image of the camera at real time or the unfolded image; the camera is used for collecting the image data. The ping-pong operation is adopted for processing the image at real time, an internal storage is used for collecting the new image while the other internal storage is used for processing the whole image collected just now, the collecting and processing operation is finished in one image field period, and the working internal storage is switched and used alternately.

The invention relates to a method for controlling a liquid crystal display, comprising a matrix of pixels arranged in crossed lines and columns and in which a switch in the state of the liquid crystal molecules, controlled by application of an electric control signal between two electrodes (50, 52) enclosing each pixel, which brings about a flow in a given direction (18), the pixel addressing being carried out by a line by line addressing either in a single step or in two steps, the first step comprising a collective addressing of at least a part of the screen in a given single texture, followed by a second step of line by line addressing, characterised in comprising, for controlling the switching of at least some of the pixels (P), a step for application to at least one adjacent pixel (58) of auxiliary electric signals wherein, depending on the direction of flow of the pixel (P) the switching of which is to be controlled, the rising or falling fronts of the auxiliary signals are temporally advanced in relation to or simultaneous with the active falling front of the electric control signal with a time offset of between 0 and several tens of microseconds at ambient temperature, such as to promote the switching of said pixel (P) for control, said auxiliary electric signals being applied in the second step when the addressing is in two steps. The invention further relates to a display.

The invention relates to the technical field of disk management, and discloses a method for optimizing a disk storage strategy of an operating system. The method for optimizing the disk storage strategy of the operating system comprises the steps of optimizing the disk storage strategy of the operating system; obtaining association rules among the processes according to historical records of the processes in the historical disk operation queue; and when the first group of processes apply for the disk space in the current disk operation queue, reserving the disk space with the set size for thesecond group of processes after the disk space applied for by the first group of processes exists, and a set association rule exists between the first group of processes and the second group of processes. By adopting the method for optimizing the disk storage strategy of the operating system, the read-write speed of a disk can be increased. The invention further discloses a device for optimizing the disk storage strategy of the operating system and intelligent equipment.

The invention discloses a double addressing periods driving method for improving addressing speed which comprises: dividing preparing period and addressing period of each subfield into first and second preparing period, first and second addressing period; entering the first preparing period first and entering the first addressing period for addressing line by line; when addressing to the middle line, starting the second preparing period and then entering the second addressing period for addressing line by line until entire display screen being addressed; entering maintaining period after addressing to maintain irradiation.

The invention provides an index file control method and a device, and electronic equipment, and the method comprises the steps: adding an image feature value in a search server into a container, and dividing the image feature value in the container into a plurality of file blocks according to a preset condition; generating an index file for each file block in the plurality of file blocks to obtaina plurality of index files in one-to-one correspondence with the plurality of file blocks, and creating a daemon process which is used for recording file sizes of the plurality of index files; judging whether the sum of file sizes of to-be-merged index files in the plurality of index files reaches a first threshold value; and under the condition that the sum of the file sizes of the to-be-mergedindex files reaches a first threshold value, performing merging operation on the to-be-merged index files by adopting the daemon process. According to the method of the invention, the loading efficiency during image search can be improved, and the time consumption of image search is further reduced.

The embodiment of the invention discloses a cloud game picture rendering method, which comprises the following steps: generating a corresponding game rendering instruction according to graphic API calling information sent by a game client; based on a preset hash function, obtaining a hash value of the game rendering instruction; determining whether the game rendering instruction is a high-frequency calling instruction or not according to the hash value; wherein the high-frequency calling instruction is a game rendering instruction of which the calling frequency reaches a first preset threshold value; and under the condition that the game rendering instruction is a high-frequency calling instruction, obtaining an index value of the game rendering instruction, and sending the index value to the game client, so that the game client searches and executes the game rendering instruction in a memory according to the index value, and renders the current frame of game picture. The method is used for solving the problems that the cloud game picture rendering calculation amount is large, the bandwidth requirement is high, and game delay is increased.

The invention concerns a panel comprising a first faceplate including at least two arrays of coplanar electrodes (Y1, Y'1) having, at each cell (4R, 4G, 4B), mutually facing edges (6, 6') separated by a constant distance (12) over a predetermined length (15) greater than the largest (14) of the dimensions of the cell in the general direction of the coplanar electrodes (Y1, Y'1); preferably, for each cell, said priming edges (6, 6') have an inclined rectilinear portion, thereby improving response time, performance and life span of the panel.

The invention discloses a file positioning method and device, equipment and a storage medium. The file positioning method comprises the steps: creating the target plug-in used for positioning a to-be-positioned file in a target webpage by creating a browser plug-in, wherein the to-be-positioned file is a project resource corresponding to the target webpage; acquiring information representing the address of the to-be-positioned file in the target webpage by using the target plug-in, and obtaining target positioning information corresponding to the to-be-positioned file; and matching the target positioning information with positioning information of a file pre-stored in a preset database, and if matching succeeds, accessing an address of the to-be-positioned file based on the target positioning information. According to the method, the information representing the address of the to-be-positioned file in the target webpage is obtained by creating and utilizing the target plug-in, so that the corresponding target positioning information is obtained, and then the address of the to-be-positioned file is accessed based on the target positioning information successfully matched with the positioning information of the pre-stored file; therefore, the addressing speed of the project resources is accelerated so as to improve the positioning efficiency.

The invention discloses an embedding-based high-resolution image expanding platform system comprising a group of camera joints CameraLink, four 16bit SSRAM with the capacity of 4M, an FPGA1 specially performing panorama expansion and Bell interpolation calculation, two 16bit SDRSDRAM with the capacity of 16M, an FPGA2 used for performing all tasks, except for the panorama expansion and Bell interpolation calculation, including display driving and Gigabit Ethernet sending and receiving, a Gigabit Ethernet interface, a display interface used for displaying images of cameras or expanded images in real time, and cameras used for image data acquisition. The SDRSDRAM are used for displaying the Gigabit Ethernet and caching the Gigabit Ethernet transmission. The images are processed in real time in a manner of table tennis, one memory region is used for a fresh segment of image acquisition, another memory region is used for processing the just acquired entire image, acquisition and processing are completed in one image field period, the operations of the memory regions are switched, and the memory regions are used alternately.