38results about How to "Improve protection characteristics" patented technology

The invention provides a transient voltage suppressor and a fabrication method thereof. The transient voltage suppressor comprises a P-type substrate, an N-type epitaxial layer, a first groove, a second groove, a first P-type diffusion region, a second P-type diffusion region, P-type epitaxial layers, an N-type injection region and a P-type injection region, wherein the N-type epitaxial layer is formed on the P-type substrate, the first groove and the second groove are formed in a surface of the N-type epitaxial layer, the first P-type diffusion region is formed on a surface of the first groove, the second P-type diffusion region is formed on a surface of the second groove, the P-type epitaxial layers are formed in the first groove and the second groove and on the N-type epitaxial layer, the N-type injection region penetrates through the P-type epitaxial layer and extends to the N-type epitaxial layer between the first groove and the second groove, and the P-type injection region is formed on a surface of the N-type injection region.

The invention relates to a protective device for an electric system. The protective device for the electric system comprises a delay type open circuit protective circuit, a negative temperature coefficient, a control switch and a rapid open circuit protective circuit, wherein the delay type open circuit protective circuit is used for carrying out open circuit protection on a circuit when the electric system has a short-circuit fault, and cannot carry out false operation on instant surge current of the electric system when the electric system is started normally, the negative temperature coefficient is used for restraining the surge current brought by charging of the capacitive load at the moment of starting, the control switch is turned off at the moment of starting of the electric system, is turned on after the starting of the electric system is accomplished, and is used for improving the surge current and eliminating influence caused by the negative temperature coefficient on conversion efficiency, and the rapid open circuit protective circuit can timely carry out operation to be opened when the electric system has the short-circuit fault, and enables the peak value of short-circuit fault current to be effectively restrained through the negative temperature coefficient. According to the protective device for the electric system, when a switch device has a short-circuit fault, the rapid open circuit protective circuit can also be timely opened to avoid impact damage caused by the surge current to devices of other portions, the protective characteristic of a power utilization system is comprehensively improved, and the defects of an existing electric power protective device are overcome.

The invention discloses a parallel MOS transistor current sharing and short circuit protection circuit, and relates to the technical fields of electronic circuits and power electronics. The parallel MOS transistor current sharing and short circuit protection circuit comprises a switching value monitoring circuit, an analog quantity monitoring circuit, a fast monitoring circuit, an MOS transistor parallel current sharing circuit, a driving circuit and a main control circuit, wherein one end of the switching value monitoring circuit is connected with the main control circuit; the other end of the switching value monitoring circuit is connected with the main control circuit and one end of the analog quantity monitoring circuit; the other end of the analog quantity monitoring circuit is connected with the fast monitoring circuit; the fast monitoring circuit is connected with the main control circuit and one end of the MOS transistor parallel current sharing circuit; and the MOS transistor parallel current sharing circuit is connected with the driving circuit and external bus voltage. The parallel MOS transistor current sharing and short circuit protection circuit realizes that each MOS transistor is equal in flowing current and switching speed, and can detect the current operating state of each MOS transistor quickly and effectively; and the parallel MOS transistor current sharing and short circuit protection circuit is simple and reliable in circuit construction and small in PCB occupation area.

An electrical device, including a semiconductor device such an electrostatic discharge protection semiconductor device, and a method for manufacturing the same. An electrostatic discharge protection semiconductor device may include a substrate and a gate in and/or over the substrate. The gate may be multi-layered, and may include a gate oxide layer and a gate electrode. An electrostatic discharge protection semiconductor device may include a source region formed in and/or over a predetermined area of the substrate on a side of the gate, and a plurality of drain regions which may be sequentially multi-layered in and/or over the substrate on an opposing side of the gate in a vertical direction. At least one drain region may be overlapped with the gate in a horizontal direction.

The invention provides a transient voltage suppressor which includes a P type substrate and an N type epitaxial layer. The N type epitaxial layer comprises a first part and a second part. The transient voltage suppressor also comprises a first P type doping area formed at the surface of a first part, a second P type doping area formed at the surface of a second part, and a P type epitaxial layer formed on the N type epitaxial layer, the first P type doping area and the second P type doping area. A first diode is formed by the P type substrate and the first part, a second diode is formed by the P type substrate and the second part, a third diode connected to the first diode is formed by the first part and the first P type doping area, a fourth diode connected to the second diode is formed by the second part and the second P type doping area, the negative electrode of the first diode is connected to the negative electrode of the second diode, and the negative electrode of the third diode is connected to the negative electrode of the fourth diode.

The invention provides a transient voltage inhibitor and a manufacturing method thereof. The transient voltage inhibitor includes a P type substrate, an N type epitaxial layer formed on the P type substrate, a first P type polysilicon, a second P type polysilicon, a first groove, a second groove, a first N type doped region formed on the inner surface of the first groove, a second N type doped region formed on the inner surface of the second groove, a third P type polysilicon formed on the surface of the first N type doped region in the first groove, and a fourth P type polysilicon formed on the surface of the second N type doped region in the second groove, wherein the first P type polysilicon and the second P type polysilicon penetrate through the N type epitaxial layer and extend to theP type substrate; the first groove and the second groove are formed on the surface, far away from the P type substrate, of the N type epitaxial layer; and the third P type polysilicon is also connected with the fourth P type polysilicon. The transient voltage inhibitor has the advantages of small device area, low process difficulty, low manufacturing cost, and higher protection performance and reliability.

The invention provides a transient voltage suppressor and a fabricating method thereof. The transient voltage suppressor comprises a P-type substrate, an N-type epitaxial layer, a first P-type doped region and a second P-type doped region, wherein the N-type epitaxial layer comprises a first part and a second part which are arranged at an interval; the first P-type doped region is formed on the surface of the first part; the second P-type doped region is formed on the surface of the second part; the P-type substrate and the first part form a first diode; the P-type substrate and the second part form a second diode; the first part and the first P-type doped region also form a third diode abutted with the first diode; the second part and the second P-type doped region also form a fourth diode abutted with the second diode; a cathode of the first diode is connected with a cathode of the second diode; and a cathode of the third diode is connected with a cathode of the fourth diode.

The invention provides a power device protection chip and a manufacturing method thereof, the chip comprising the following steps: a substrate of a first conductivity type; A first epitaxial layer ofa second conductivity type; A first buried layer of a first conductivity type and a second buried layer of a second conductivity type, formed in the first epitaxial layer; A second epitaxial layer ofthe first conductivity type; A first injection region of a first conductivity type and a second injection region of a second conductivity type formed on an upper surface of the second epitaxial layer,and the first injection region is connected to the second injection region; A polycrystalline silicon layer penetrating the second epitaxial layer and connected to the first implanted region and thefirst buried layer, respectively; A dielectric layer formed on an upper surface of the second epitaxial layer; A first electrode including a first portion penetrating the dielectric layer and extending to the second implantation region and a second portion formed on a surface of the dielectric layer; A second electrode formed on a lower surface of the substrate. The invention can improve device performance and reduce device cost.

The invention discloses a low-capacitance TVS (transient voltage suppressor) diode and a manufacture method thereof; the low-capacitance TVS diode is characterized in that three TVSs are integrated and connected in parallel through process modifications based on traditional TVSs, parasitic capacitance of a device is reduced, the device has small area, the process has low difficulty, and device manufacturing cost is reduced; the modified TVS device has improved protective property and reliability.

The invention relates to a transient voltage suppressor and a manufacturing method thereof. The transient voltage suppressor comprises a P-type substrate, a first N-type epitaxy formed on the P-type substrate, a second P-type epitaxy formed on the surface of the first N-type epitaxy, a trench which penetrates through the P-type epitaxy and extends into first N-type epitaxy, a first P-type injection region formed on the surface of the trench of the first N-type epitaxy, silicon oxide formed on the surface of the first P-type injection region on the side wall of the trench and extending to the surface of the side wall of the trench of the P-type epitaxy, polycrystalline silicon formed on the first P-type injection region at the bottom of the trench and the surface of the silicon oxide, a second N-type epitaxy formed in the trench and on the polycrystalline silicon and a second P-type injection region is formed on the surface of the second N-type epitaxy.

The invention relates to a device for observing overpressure of a mooring rope for constructional engineering, belongs to the field of buildings, and particularly relates to a mooring rope protector for a building. The mooring rope protector for the building comprises a shell, a first connecting piece, a second connecting piece and a snapping piece, wherein the first connecting piece is connected with the second connecting piece through the snapping piece; the shell sleeves the outsides of the first connecting piece, the second connecting piece and the snapping piece; and after the snapping piece is snapped off, the shell bears a tensile force between the first connecting piece and the second connecting piece. By the design of the snapping piece which can be snapped off, use safety of the mooring rope can be guaranteed effectively, before the tensile force reaches a rated snapping-off force of the mooring rope, the snapping piece is snapped off at first, then whether the mooring rope is used in an overload manner can be observed effectively, and the protective feature of the mooring rope is improved. By the design of a weak link arranged on the mooring rope, whether the mooring rope is in an overpressure state or not when used can be judged, and therefore, the service life of the mooring rope in a using process can be judged.

The invention provides a protection device for a power component and a manufacturing method thereof, and relates to the technical field of semiconductor devices. The method comprises firstly, providing an N-type substrate in which a first silicon oxide layer is formed, and removing the bottom of the first silicon oxide layer by etching; secondly, successively forming a first P-type epitaxial layer, an N-type epitaxial layer and a second P-type epitaxial layer, forming a silicon oxide underlayer on a lower surface of the first P-type epitaxial layer; forming a second silicon oxide layer on thesidewalls of grooves in the first P-type epitaxial layer, the N-type epitaxial layer and the second P-type epitaxial layer; then forming a third silicon oxide layer and a metal layer to form a first electrode and a second electrode; and finally, forming a silicon oxide passivation layer on the surface. The method realizes the integration of TVS by using a buried layer process, improves the anti-surge capability of a device, reduces the area of the device, realizes the small-sized package of a high-end IC, and solves the low anti-surge capability and large device area in the prior art.

The invention provides a current protection chip and a manufacturing method thereof. The current protection chip comprises a substrate of a first conductivity type; afirst epitaxial layer of a secondconductivity type; afirst buried layer of a first conductivity type and a second buried layer of a second conductivity type, formed in the first epitaxial layer; asecond epitaxial layer of a first conductivity type formed on a surface of the first epitaxial layer; afirst injection region of a second conductivity type and a second injection region of the first conductivity type, formed on a surfaceof the second epitaxial layer, and the second injection region is located in the first injection region; apolycrystalline silicon layer connected to the first implantation region and the first buriedlayer, respectively; adielectric layer formed on an upper surface of the second epitaxial layer; afirst electrode including a first portion penetrating the dielectric layer and extending to the second implantation region and a second portion formed on a surface of the dielectric layer; asecond electrode formed on a lower surface of the substrate and connected to the substrate. The invention can improve device performance and reduce device cost.

The invention provides a current protection chip and a manufacturing method thereof, comprising the following steps: a substrate of a first conductivity type; A first epitaxial layer of a first conductivity type; A first buried layer and a second buried layer of a first conductivity type formed in the first epitaxial layer; A second epitaxial layer of a second conductivity type formed on an uppersurface of the first epitaxial layer; A first injection region of a first conductivity type and a second injection region of a second conductivity type, and the first injection region is connected tothe second injection region; A polycrystalline silicon layer penetrating the second epitaxial layer and connected to the first implanted region and the second buried layer, respectively; A dielectriclayer formed on an upper surface of the second epitaxial layer; A first electrode including a first portion connected to the first injection region and the second injection region through the dielectric layer, and a second portion formed on a surface of the dielectric layer; A second electrode formed on a lower surface of the substrate. The invention can improve device performance and reduce device cost.

The invention discloses a groove-type transient voltage suppressor and a manufacturing method thereof. According to the manufacturing method, a first substrate of a first conduction type and a secondsubstrate of a second conduction type are etched and heated to form a bonding semiconductor structure, the bonding semiconductor structure comprises at least three binding semiconductor columns, conduction types of two adjacent semiconductor columns are opposite, the semiconductor columns comprise first connecting columns, second connecting columns and interval columns, the first connecting columns are used for connecting with first metal layers, the second connecting columns are used for connecting with second metal layers, and the interval columns are positioned among the first connecting columns and the second connecting columns. The groove-type transient voltage suppressor at least comprises two serially connected and abutted diodes, so that a bi-directional protection function is achieved. A PN knot interface shortcoming of the bonding semiconductor structure is less, so that electric leakage of the groove-type transient voltage suppressor is low, and the protective characteristics and the reliability of the groove-type transient voltage suppressor are effectively improved.