38results about How to "Improve protection characteristics" patented technology

The invention provides a transient voltage suppressor and a manufacturing method thereof. The suppressor includes a substrate of a first conductivity type; afirst epitaxial layer of a second conductivity type grown on an upper surface of the substrate; adiffusion layer of a second conductivity type formed on a lower surface of the substrate; asecond epitaxial layer of a second conductivity type including a first portion disposed on an upper surface of the first epitaxial layer, the doping concentration of the second epitaxial layer being higher than the doping concentration of the first epitaxial layer; afirst implantation region of a second conductivity type formed on an upper surface of the first portion, the doping concentration of the first implantation region being higher than the doping concentration of the second epitaxial layer; afirst electrode electrically connected to the first injection region; and a second electrode electrically connected to the diffusion layer. This scheme can improve device performance and reduce device cost.

The invention provides a power device protection chip and a manufacturing method thereof, comprising: a substrate of the first conductivity type; a first epitaxial layer of the first conductivity type grown on the upper surface of the substrate; a buried layer of the first conductivity type layer, formed in the first epitaxial layer; a second epitaxial layer of the second conductivity type, formed on the upper surface of the first epitaxial layer; a third epitaxial layer of the second conductivity type, penetrating through the second epitaxial layer and connected to the buried layer; the first injection region of the first conductivity type is formed in the second epitaxial layer and connected to the buried layer and the third epitaxial layer; a dielectric layer, the dielectric layer comprising a first portion located on the upper surface of the second epitaxial layer connected to the first portion and extending through the second epitaxial layer to a second portion of the first epitaxial layer; a polysilicon layer extending through the first portion to within the third epitaxial layer. The invention can improve device performance and reduce device cost.

The invention provides a protection device for a power component and a manufacturing method thereof, and relates to the technical field of semiconductor devices. The method comprises firstly, providing an N-type substrate in which a first silicon oxide layer is formed, and removing the bottom of the first silicon oxide layer by etching; secondly, successively forming a first P-type epitaxial layer, an N-type epitaxial layer and a second P-type epitaxial layer, forming a silicon oxide underlayer on a lower surface of the first P-type epitaxial layer; forming a second silicon oxide layer on thesidewalls of grooves in the first P-type epitaxial layer, the N-type epitaxial layer and the second P-type epitaxial layer; then forming a third silicon oxide layer and a metal layer to form a first electrode and a second electrode; and finally, forming a silicon oxide passivation layer on the surface. The method realizes the integration of TVS by using a buried layer process, improves the anti-surge capability of a device, reduces the area of the device, realizes the small-sized package of a high-end IC, and solves the low anti-surge capability and large device area in the prior art.

The invention discloses a parallel MOS transistor current sharing and short circuit protection circuit, and relates to the technical fields of electronic circuits and power electronics. The parallel MOS transistor current sharing and short circuit protection circuit comprises a switching value monitoring circuit, an analog quantity monitoring circuit, a fast monitoring circuit, an MOS transistor parallel current sharing circuit, a driving circuit and a main control circuit, wherein one end of the switching value monitoring circuit is connected with the main control circuit; the other end of the switching value monitoring circuit is connected with the main control circuit and one end of the analog quantity monitoring circuit; the other end of the analog quantity monitoring circuit is connected with the fast monitoring circuit; the fast monitoring circuit is connected with the main control circuit and one end of the MOS transistor parallel current sharing circuit; and the MOS transistor parallel current sharing circuit is connected with the driving circuit and external bus voltage. The parallel MOS transistor current sharing and short circuit protection circuit realizes that each MOS transistor is equal in flowing current and switching speed, and can detect the current operating state of each MOS transistor quickly and effectively; and the parallel MOS transistor current sharing and short circuit protection circuit is simple and reliable in circuit construction and small in PCB occupation area.

The invention provides a current protection chip and a manufacturing method thereof. The current protection chip comprises a substrate of a first conductivity type; afirst epitaxial layer of a secondconductivity type; afirst buried layer of a first conductivity type and a second buried layer of a second conductivity type, formed in the first epitaxial layer; asecond epitaxial layer of a first conductivity type formed on a surface of the first epitaxial layer; afirst injection region of a second conductivity type and a second injection region of the first conductivity type, formed on a surfaceof the second epitaxial layer, and the second injection region is located in the first injection region; apolycrystalline silicon layer connected to the first implantation region and the first buriedlayer, respectively; adielectric layer formed on an upper surface of the second epitaxial layer; afirst electrode including a first portion penetrating the dielectric layer and extending to the second implantation region and a second portion formed on a surface of the dielectric layer; asecond electrode formed on a lower surface of the substrate and connected to the substrate. The invention can improve device performance and reduce device cost.

The invention provides a transient voltage suppressor and a fabrication method thereof. The transient voltage suppressor comprises a P-type substrate, an N-type epitaxial layer, a first groove, a second groove, a first P-type diffusion region, a second P-type diffusion region, P-type epitaxial layers, an N-type injection region and a P-type injection region, wherein the N-type epitaxial layer is formed on the P-type substrate, the first groove and the second groove are formed in a surface of the N-type epitaxial layer, the first P-type diffusion region is formed on a surface of the first groove, the second P-type diffusion region is formed on a surface of the second groove, the P-type epitaxial layers are formed in the first groove and the second groove and on the N-type epitaxial layer, the N-type injection region penetrates through the P-type epitaxial layer and extends to the N-type epitaxial layer between the first groove and the second groove, and the P-type injection region is formed on a surface of the N-type injection region.

The invention provides a transient voltage suppressor and a fabricating method thereof. The transient voltage suppressor comprises a P-type substrate, an N-type epitaxial layer, a first P-type doped region and a second P-type doped region, wherein the N-type epitaxial layer comprises a first part and a second part which are arranged at an interval; the first P-type doped region is formed on the surface of the first part; the second P-type doped region is formed on the surface of the second part; the P-type substrate and the first part form a first diode; the P-type substrate and the second part form a second diode; the first part and the first P-type doped region also form a third diode abutted with the first diode; the second part and the second P-type doped region also form a fourth diode abutted with the second diode; a cathode of the first diode is connected with a cathode of the second diode; and a cathode of the third diode is connected with a cathode of the fourth diode.

The invention relates to a transient voltage suppressor and a manufacturing method thereof. The transient voltage suppressor includes an N-type substrate, a first trench and a second trench formed onthe surface of the N-type substrate, first and second P-type diffusion regions formed on the surfaces of the first trench and the second trench, an N-type epitaxy formed on the surfaces of the N-typesubstrate and the first and second P-type diffusion regions, a silicon oxide layer formed on the N-type epitaxy, two third trenches which pass through the N-type epitaxy and extends to the N-type substrate and two sides of the first P-type diffusion region, two fourth trenches which pass through the N-type epitaxy and extends to the N-type substrate and two sides of the second P-type diffusion region, silicon oxide in the third and the fourth trenches, a first through hole corresponding to the first trench, a second through hole corresponding to the second trench, a P-type injection region which is formed at the surface of the N-type epitaxy, an N-type injection region formed on the surface of the P-type injection region, an opening corresponding to the N-type injection region, and a P-type injection layer formed at the other side of the N-type substrate.

The invention provides a transient voltage inhibitor and a manufacturing method thereof. The transient voltage inhibitor includes a P type substrate, an N type epitaxial layer formed on the P type substrate, a first P type polysilicon, a second P type polysilicon, a first groove, a second groove, a first N type doped region formed on the inner surface of the first groove, a second N type doped region formed on the inner surface of the second groove, a third P type polysilicon formed on the surface of the first N type doped region in the first groove, and a fourth P type polysilicon formed on the surface of the second N type doped region in the second groove, wherein the first P type polysilicon and the second P type polysilicon penetrate through the N type epitaxial layer and extend to theP type substrate; the first groove and the second groove are formed on the surface, far away from the P type substrate, of the N type epitaxial layer; and the third P type polysilicon is also connected with the fourth P type polysilicon. The transient voltage inhibitor has the advantages of small device area, low process difficulty, low manufacturing cost, and higher protection performance and reliability.