14 results about "Memory redundancy" patented technology

The invention discloses a kernel-level heterogeneous collaborative AI reasoning method and device, equipment and a storage medium, and relates to the field of AI reasoning acceleration. When the KDS receives a reasoning request submitted by a user space, generating a cross-device plan list according to a global system resource state and issuing the cross-device plan list to the HCEE; the HCEE drives the corresponding target execution equipment according to the task execution sequence, reads the data information from the UCMP, or restores intermediate / result data reasoned and output by the target execution equipment; after reasoning of the plan list is completed, the kernel space triggers an event notification mechanism, and a user process of the user space is awakened; and the user process directly reads the reasoning result from the UCMP. According to the scheme, deep collaboration of task scheduling, memory management and equipment execution is realized on a Linux kernel level, the problems of high overhead, resource islands, memory redundant copy, extensive scheduling granularity and the like of a user mode reasoning framework system are solved, and end-to-end low-delay, high-throughput and high-energy-efficiency AI reasoning acceleration is realized.

This invention provides a memory and its address setup time tracking method, belonging to the field of microelectronics technology. It includes: a memory redundancy array arranged around the periphery of the memory array; row address redundancy decoders and column address redundancy decoders, which respectively track the maximum delay time of row address setup time and column address setup time to obtain first and second delay tracking signals; and a logic processing unit, which logically processes the first and second delay tracking signals and read / write control signals to generate read / write trigger signals for performing read / write operations on the target memory cell. Beneficial effects: By introducing row and column address redundancy decoders to track the maximum delay of the maximum delay of row and column address setup time, and logically processing this delay with the read / write control signals to generate read / write trigger signals for the target address memory cell, it simultaneously ensures that read / write operations are not triggered on non-target address memory cells during the address signal decoding delay, avoiding memory erroneous reads and writes and improving reliability.

The invention discloses a thermal memory enhanced neural network numerical control machine tool thermal error prediction method and system, and relates to the technical field of intelligent manufacturing and machine tool thermal error compensation. S1, temperature difference sensitive point data and corresponding thermal error data of a machine tool under different working conditions are collected; s2, performing standardization processing on the data in the S1, and reconstructing input features into a time sequence tensor form; and S3, constructing a thermal memory library. According to the thermal memory enhanced neural network numerical control machine tool thermal error prediction method and system, temperature difference sensitive point data and thermal error data under multiple working conditions of a machine tool are collected, a thermal memory library containing diversity control, time decay and an adaptive forgetting mechanism is constructed after preprocessing, a double-layer GRU neural network and a high-error sample weighted playback strategy are combined, and the thermal error prediction accuracy of the machine tool is improved. High-precision prediction and real-time compensation of thermal errors are achieved, online incremental learning and rapid deployment are supported, and the problems that an existing model forgets once a high-error sample is passed, memory redundancy exists, and precision drifts exist are effectively solved.

The invention relates to a neural network model lightweight reasoning method and device, a medium and equipment. The neural network model lightweight reasoning method comprises the following steps: floating point model preparation: obtaining a floating point neural network model obtained based on deep learning framework training; model verification: performing operator compatibility verification on the floating point neural network model to ensure that the operator type supports the embedded device; calibration data preparation: preparing a batch of calibration data, and performing data preprocessing consistent with the reasoning stage of the floating point neural network model on the calibration data; according to the method, three key steps of model structure optimization, quantization after training and hardware adaptation compiling are deeply fused into a continuous processing flow, so that intermediate calculation and memory redundancy caused by traditional segmentation optimization are effectively reduced, and reasoning delay and resource occupation of the model on embedded equipment are remarkably reduced; and the deployment efficiency and the system performance are improved.

This application provides a data query method, apparatus, device, and medium. By dividing the query term sequence into a first query term and a second query term, and determining the corresponding semantic nearest neighbor set and query condition probability for each second query term based on its prefix in the query term sequence, and combining the text content of the first query term, the query term sequence is matched with each stored term sequence indicated by the target multi-way tree. This significantly improves the hit rate and reuse rate of cached key-value vectors, effectively reuses key-value vectors of terms with the same or similar semantics but different expressions, and significantly reduces memory usage while ensuring generation quality and cache hit rate. This improves the overall efficiency and scalability of large language model inference, and achieves synergistic optimization of large language models in three dimensions: memory efficiency, throughput performance, and generation quality. It effectively reduces the problems of low cache hit rate, serious memory redundancy, and unstable generation quality in related technologies.

The application discloses an astronomical cross-identification confidence calculation method for memory access optimization, and steps are as follows: S1, flattening the astronomical cross-identification result into a one-dimensional main source index array and a one-dimensional candidate source index array; S2, constructing an offset array; S3, respectively constructing a plurality of columnar one-dimensional continuous celestial body attribute arrays of main star table celestial bodies and candidate star table celestial bodies; S4, generating an unnormalized logarithmic score array through candidate pair level linear scanning calculation; S5, obtaining the normalized probability of each candidate pair in a candidate group and the total confidence of the candidate group through candidate group level segmented reduction normalization; S6, judging based on a set threshold value, and outputting a candidate pair with high reliability; the method solves the problems of low memory access efficiency and memory redundancy in astronomical big data calculation under the premise of keeping 99.9% of the decision consistency rate of the traditional method, reduces the data structure redundancy caused by complex nested objects, and improves the advantages of memory access and calculation efficiency under the pressure of large-scale candidate bodies.

The invention relates to a shared cache-based data processing method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: if a data pointer of target data is not queried in a local cache, acquiring the target data and a corresponding data identifier from a system disk; the data pointer is used for indicating a storage address of the target data in the shared cache; querying target data in a shared cache according to the data identifier; and creating a data pointer of the target data in the local cache based on the storage address of the target data in the shared cache. Therefore, data cache copies do not need to be independently maintained in the local caches, and the problem of memory redundancy caused by the fact that the local caches of the back-end processes repeatedly store the same data in a traditional mode is avoided; and the shared cache only undertakes a data storage function, so that lock conflicts and visibility judgment complexity caused by a multi-version mechanism are avoided, and the stability of system performance is guaranteed.

The invention relates to the technical field of computers, discloses a multi-source heterogeneous data three-dimensional visualization engine optimization method and system adaptive to a port scene, and aims to solve the problems of high rendering overhead, video memory redundancy and data synchronization lag of a port storage yard. The method comprises the following steps: constructing a container low-model geometry and loading the container low-model geometry into a GPU static video memory; establishing a dynamic attribute buffer area to store real-time pose, color and texture indexes; the access port TOS system asynchronously updates buffer area entries; in the rendering stage, an instantiated rendering instruction is called to complete parallel drawing. The system comprises a geometry prototype construction module, a dynamic attribute buffer area management module, a data integration distribution module, an instantiation rendering driving module and a video memory monitoring recovery module. Through adoption of the scheme, the rendering call frequency can be remarkably reduced, the video memory utilization rate is optimized, high-real-time synchronization of a physical port and a digital twin scene is realized, and the interaction performance and the data bearing capacity of a system are improved.

The invention relates to a data page deleting method and device, a processor and a readable storage medium. The method comprises the following steps: controlling a plurality of threads in a storage engine to execute lock grabbing operation under the condition of detecting that a memory data page deletion requirement exists in a storage system, and determining a plurality of scheduling threads based on a lock grabbing operation result of each thread; a memory of the storage system comprises a plurality of memory data page indexes, each memory data page index corresponds to at least one memory data page to be processed, and each memory data page index is correspondingly provided with a lock; according to the lock preempted by each scheduling thread, controlling each scheduling thread to screen the to-be-processed memory data page under the data index corresponding to the preempted lock, and determining a to-be-deleted target memory data page under each data index; and deleting the target memory data page. By adopting the method, memory redundant resources can be released in time in a high-concurrency scene, and the memory pressure of the storage system is relieved, so that the core read-write performance of the storage system is improved.

The invention discloses a tri-dexel model based on a linked list and a processing simulation method, and belongs to the technical field of precision processing, the model adopts a three-level linked list structure of line segment node-ray node-grid node to replace a traditional array to construct dexel grids in X, Y and Z directions; the method comprises the following steps: initializing a model to construct workpiece digital twinning; calculating a tool-workpiece meshing area; dynamically updating line segments through in-situ addition, deletion and modification operations of linked list nodes, realizing material removal simulation, and synchronizing data in three directions; and finally, visualization and result output are carried out. According to the tri-dexel model based on the linked list and the processing simulation method, through dynamic storage of the linked list and three-direction collaborative management, the problems that a traditional method is low in dynamic operation efficiency, large in memory redundancy and poor in collaboration are solved, and the real-time performance, precision and memory efficiency of processing simulation are remarkably improved.

Techniques described herein provide memory redundancy. For example, the memory block for each pixel can be partitioned into multiple memory bins, and the number of memory bins can be larger than the number of time bins. Once a faulty memory cell is identified, an address associated with the memory bin that has the faulty memory cell can be skipped by an address generator. As such, the faulty memory cell is not used to store time-of-fight (ToF) information.

The invention relates to the technical field of deep learning reasoning, in particular to a calculation method of a Conv2D operator on a TPU chip. The method comprises the following steps: decomposing a size convolution kernel to be processed into 1 * 1 sub-kernels; dynamically determining an optimal block size and a segmentation strategy based on the VMEM capacity, the convolution parameter and the input size on the TPU chip; on the basis of convolution parameter features, different calculation scenes are adapted through a hierarchical multi-branch optimization strategy, and a calculation adaptation path of the 1 * 1 sub-kernel is determined; according to the optimal block size and the adaptive path, matrix multiplication is executed, and a calculation result is obtained; and accumulating all calculation results to obtain the final output of the Conv2D operator. According to the method, the problems that memory redundancy expansion is caused by explicit im2col, and overflow is easily caused by dependence on a transfer space can be solved; serial execution of data transmission and calculation; and the scene adaptability of a fixed partitioning strategy is weak.

The present application relates to the technical field of deep learning inference, and particularly relates to a calculation method of a Conv2D operator on a TPU chip. The method comprises: decomposing a size convolution kernel to be processed into a plurality of 1x1 sub-kernels; dynamically determining an optimal block size and a segmentation strategy based on VMEM capacity on the TPU chip, convolution parameters and input size; determining a calculation adaptation path of the 1x1 sub-kernels by adapting different calculation scenarios through a hierarchical multi-branch optimization strategy based on convolution parameter characteristics; performing matrix multiplication operation according to the optimal block size and the adaptation path to obtain a calculation result; and accumulating all the calculation results to obtain the final output of the Conv2D operator. The present application can solve the problems of memory redundancy expansion caused by explicit im2col, overflow caused by dependence on a transfer space, serial execution of data transmission and calculation, and weak adaptability of a fixed block strategy scenario.

The application discloses a tri-dexel model based on a linked list and a machining simulation method, and belongs to the technical field of precision machining. The model adopts a three-level linked list structure of a line segment node, a ray node and a grid node to replace a traditional array to construct a dexel grid in X, Y and Z directions. The method comprises the following steps: initializing the model to construct a workpiece digital twin; calculating a tool-workpiece engagement area; dynamically updating a line segment through in-situ adding, deleting and modifying operations of the linked list node, realizing material removal simulation, and synchronizing three-direction data; and finally, visualizing and outputting results. The tri-dexel model based on the linked list and the machining simulation method provided by the application dynamically store through the linked list and cooperatively manage in three directions, overcome the problems of low dynamic operation efficiency, large memory redundancy and poor cooperativeness of the traditional method, and significantly improve the real-time performance, precision and memory efficiency of the machining simulation.