38results about How to "Reduce storage capacitance" patented technology

The invention provides an array substrate. The array substrate comprises a substrate body, wherein a signal transmission line, a first insulating layer, a second insulating layer, a pixel electrode layer and a public electrode layer are located on the substrate body, the first insulating layer is located between the signal transmission line and the public electrode layer, the second insulating layer is located between the pixel electrode layer and the public electrode layer, the dielectric constant of the first insulating layer is smaller than or equal to that of the second insulating layer, and the signal transmission line is electrically connected with the public electrode layer. By means of the array substrate, the parasitic capacitance between the signal transmission line and the public electrode layer or the pixel electrode layer is reduced. Due to the reduction of the parasitic capacitance, the reduction of loads on a touch control panel is facilitated, the charging time of a touch control electrode is shortened as well, and the touch control sensitivity of the touch control panel is improved. The invention further provides a display panel and a display device.

A power factor correction (PFC) circuit includes an inductor, a diode, a storage capacitor, a switch and a control unit. The input power has a voltage fluctuation V1. The storage component absorbs a first voltage fluctuation and a switch regulation circuit absorbs a second voltage fluctuation V2. Thus output voltage from the PFC circuit is not a conventional constant voltage but a voltage of a great ripple. The PFC circuit further has a harmonic regulation unit. The harmonic regulation unit generates a voltage signal containing 3rd harmonic. The control unit receives a feedback signal and the voltage signal containing 3rd harmonic to generate a reference to the inductor current. Therefore, the inductor current contains 3rd harmonic. Thus power fluctuation absorbed and released by the capacitor is smaller. As a result energy storage capacitance can be reduced significantly.

The disclosed technology discloses an array substrate and a liquid crystal display panel. The array substrate comprises: a base substrate; a gate line and a data line formed on the base substrate, the gate line and the data line defining a plurality of pixel regions; and a first electrode layer and a second electrode layer formed in each pixel region; and an insulating layer provided between the first electrode layer and the second electrode layer. The first electrode layer, the insulating layer and the second electrode layer are laminated on the base substrate in this order. The first electrode layer is provided with a plurality of first apertures therein, and the first electrode layer comprises a plurality of first electrode portions located between the plurality of first apertures.

The invention discloses an array substrate and a manufacturing method of the array substrate as well as a display device. The array substrate comprises a pixel array composed of pixel units which are arrayed in a matrix manner, and a plurality of grid electrode wires which extend along the transverse direction of the pixel array; a routing region is arranged between every two adjacent rows of the pixel units; types of each routing region comprise a first routing region, a second routing region and a third routing region; each routing region is provided with a data line; at most one grid electrode output line is arranged in each second routing region, and is connected with the corresponding grid electrode line; each third routing region is provided with two data lines located on different thin film layers; the distance between the two data lines of each third routing region along the transverse direction of the pixel units is less than or equal to 0. According to the array substrate disclosed by the invention, the distance between the grid electrode output line and each data line can be increased, voltage coupling on the data lines is reduced, and the bright spot problem is solved; meanwhile, the distance between the two data lines of each third routing region is reduced, and influences on the picture quality effect can be weakened.

An array substrate, a display apparatus, and a manufacturing method for the array substrate are provided. The array substrate comprises: an underlayer substrate (1); scanning lines (12) and data lines (11) that cross each other and are located on the underlayer substrate (1), the scanning lines (12) and the data lines (11) defining multiple pixel areas; multiple thin film transistors, arranged in an array and respectively located in each pixel area; pixel electrodes (10), located in the pixel areas, and a common electrode (3); an insulation layer (13), located between the common electrode (3) and the scanning lines (12), an projection of the scanning lines (12) on the underlayer substrate (1) at least partially overlapping an projection of a common electrode line (2) on the underlayer substrate (1).

The invention relates to an array substrate, a manufacturing method thereof and a liquid crystal display with a wide viewing angle. The array substrate includes a base substrate and a plurality of pixel regions, and also includes an organic transparent insulating layer formed between the passivation layer and the pixel electrodes. The manufacturing method includes: forming a common electrode, a common electrode line, and a pattern of a thin film transistor switch on a base substrate; depositing a passivation layer; forming an organic transparent insulating layer on the passivation layer, and forming an organic layer via hole and a passivation layer A via hole: a pattern of the pixel electrode is formed on the organic transparent insulating layer, the pattern of the pixel electrode has a plurality of gaps, and the pixel electrode is connected to the thin film transistor switch through the organic layer via hole and the passivation layer via hole. The liquid crystal display of the present invention includes the array substrate of the present invention. The invention adopts the technical means of adding an organic transparent insulating layer between the pixel electrode and the passivation layer, increases the thickness of the film layer between the pixel electrode and the common electrode, can effectively reduce the storage capacitance and reduce afterimages.

The embodiment of the invention provides a CMOS image sensor and relates to the technical field of semiconductors. The CMOS image sensor can achieve high-sensitivity and high-speed responses. Each pixel unit of the CMOS image sensor comprises a P type semiconductor substrate, a first N type ion layer on the upper portion of the P type semiconductor substrate, a P trap surrounding the first N type ion layer, a second N type ion layer, a third N type ion layer, a first P type ion layer and a second P type ion layer, wherein the second N type ion layer, the third N type ion layer, the first P type ion layer and the second P type ion layer are arranged on the upper portion of the first N type ion layer; the first P type ion layer and the second P type ion layer are spaced by the second N type ion layer, the second N type ion layer and the third N type ion layer are spaced by the second P type ion layer, the doping concentration of the second N type ion layer and the doping concentration of the third N type ion layer are larger than the doping concentration of the first N type ion layer, and the doping concentration of the first P type ion layer and the doping concentration of the second P type ion layer are between the doping concentration of the P trap and the doping concentration of the P type semiconductor substrate. The CMOS image sensor is used for sensor manufacturing.

The invention discloses a pixel structure, an array substrate and a display device. The pixel structure comprises a first electrode and a second electrode, wherein the first electrode comprises a plurality of first electrode parts and a plurality of first gaps located between the adjacent first electrode parts, the second electrode comprises a plurality of parallel strip-shaped second electrode parts and a plurality of second gaps located between the adjacent second electrode parts, the downward perpendicular projection of each first electrode part is overlapped with the downward perpendicular projection of each second electrode part, the second electrode comprises third electrode parts, and each second electrode part is connected with the adjacent electrode part through one third electrode part. The array substrate comprises the pixel structure. The display device comprises the array substrate. According to the technical scheme, storage capacitance is reduced, the second electrode is designed in a narrow gap patterning mode, and on the basis of reducing the storage capacitance, high transmittance and high technological yield are maintained.

The invention discloses a display panel and a display device, which belong to the technical field of display. The display panel includes scanning lines, data lines, pixel electrodes and a black matrix. The black matrix includes an externally expanded black matrix. The first black matrix is ​​connected, the scan line and the data line intersect to define the sub-pixel, the pixel electrode is arranged in the sub-pixel, the pixel electrode includes a first part and a second part that are connected to each other, and the first part includes a plurality of parts extending along the third direction. The first strip electrodes, the plurality of first strip electrodes are not connected, the first strip electrodes include the first subtype strip electrodes and the second subtype strip electrodes, the first subtype strip electrodes and the second subtype strip electrodes One of the strip-like electrodes overlaps with the externally expanded black matrix, and the other does not overlap with the expanded black matrix. The invention reduces the storage capacitance between the pixel electrode and the common electrode, improves the charging capability of the pixel, and improves the display effect.

An organic light-emitting diode (OLED) array substrate and an OLED display device are provided. The OLED array substrate includes a plurality of driving circuits of a plurality of sub-pixels using a mirror symmetrical structure, and a plurality of reset signal lines and a plurality of power signal lines extending along a same direction. By sharing each of the reset signal lines and each of a plurality of first vias, and sharing each of the power signal lines and each of a plurality of second vias, about half of lines of power signal lines, reset signal lines, and vias are saved. Therefore, room for increasing pixels per inch (PPI) is provided, facilitating realizing high PPI panel designs.