Three-dimensional 3D circuit (60) comprising: a first layer (61-1) comprising at least one first
memory cell (65-0); a second layer (62-1) above the first layer (61-1), wherein the second layer (62-1) comprises at least one second
memory cell (64-0), the second layer (62-1) being arranged in a vertical stack with the first layer (61-1) above the first layer (61-1); a third layer (61-X) below the first layer (61-1), wherein the third layer (61-X) comprises at least one third
memory cell (65-4, 65-5, 65-6, 65-7) arranged below the first layer (61-1); a fourth layer (62-Y) above the second layer (62-1), wherein the fourth layer (62-Y) comprises at least one fourth memory
cell (64-4, 64-5, 64-6, 64-7) which is arranged above the second layer (62-1);and a word line (63-1) shared by the first memory
cell (65-0), the second memory
cell (64-0), the third memory cell (65-4, 65-5, 65-6, 65-7) and the fourth memory cell (64-4, 64-5, 64-6, 64-7), wherein the word line (63-1) is a horizontal word line, the horizontal word line extending in a horizontal direction perpendicular to the direction of the vertical stack; and wherein the horizontal word line is arranged vertically between the first memory cell (65-0) and the second memory cell (64-0).