The invention discloses a
field programmable gate array (FPGA)-based KeyStone transformation
range migration correction method, which comprises the following steps of: transposing data in a
double data rate 3 (DDR3) to a range direction, performing inverse Fourier transformation in the range direction, transposing the data to an
azimuth direction and storing the data back to the DDR3;
zero padding is carried out on the head and the
tail of data in the DDR3 by controlling the dual-port RAM; the data size and the
signal parameters are transmitted into a
chirp generation module to generate
phase compensation so as to calculate a stepping factor; multiplying the zero-filled data by a stepping factor, and performing inverse
Fourier transform along the
azimuth to obtain a first transform result; carrying out conjugate
processing on the stepping factor and carrying out inverse
Fourier transform along the
azimuth direction to obtain a second transformation result; multiplying the first transformation result and the second transformation result, and performing Fourier transformation along the azimuth to obtain a third transformation result; multiplying the third transformation result by a stepping factor, and performing inverse
Fourier transform along the azimuth to obtain a fourth transformation result; and sampling the fourth transformation result in the
azimuth direction and carrying out Fourier transformation along the distance direction to obtain a correction result. The method is high in correction efficiency.