A method and circuit for a high speed interface that enables the integration of several Content Addressable memories into a larger, Combined
Content Addressable Memory with only an insignificant
delay in the original
response time of the individual memories. The interface provides connections to the
Bus system only and no connection between different
CAM devices of the
system is needed, whereby the combination of one
CAM and one
CAM interface in a single device, such as a
chip is enabled. Such chips may be used as modules for increasing the CAM Memory by directly attaching them to the
Bus System without any additional interface, as known for standard memory chips such as RAM. The inventive interface may also be used for creating a hierarchical structure within a CAM device by dividing the memory cells in groups, each group being interfaced to the larger combined CAM device via an interface according to the invention. In such a structure the
priority function in each group operates on a smaller number of cells and due to the relatively small number of gates necessary for making the interface the implementation of a CAM device with a reduced number of gates is facilitated. In a combined CAM device several CAMs are connected to an
Address Bus and to a Data
Bus via their respective interfaces. In the Read and Write mode, the interface will connect the two sets of lines and thus be transparent for the Read or Write operation. In the search mode (Content
Addressing mode), the Interface will select and set a number of lines of the Data Bus according to the CAM response so as to output the address of one matching
cell that is the highest in a predefined direction. The interface circuit adds the logic functions and lines necessary to expand the Content addressable functions of the CAM module to a larger range of addresses, sets an additional number of
bus lines in order to write the address of the
cell within that larger range and checks that no other
cell with a higher address responds throughout the
system by masking the bits of the CAM address if they would change the address of a cell with a higher address. In this way the whole ensemble of CAMs is capable of functioning as a single CAM of larger size.