The invention relates to a TSN (
Time Sensitive Network)
timestamp recovery method based on an FPGA (
Field Programmable Gate Array), which belongs to the technical field of TSNs and comprises the following steps of: S1, collecting synchronous messages of different TSN nodes in parallel by multiple ports of the FPGA, and analyzing
timestamp data by taking a message serial number as an
anchor point; s2, constructing an incomplete
timestamp matrix and a
mask matrix by adopting a time sliding window mechanism, and automatically marking
missing data; s3, a random index set is generated through LFSR, and matrix sparse sampling is achieved through a
bitmap judgment unit; and S4, based on an FPGA accelerated CUR
matrix decomposition algorithm, solving a pseudo-inverse matrix through parallel MGS-
QR decomposition, and reconstructing a complete timestamp matrix through block parallel matrix chain multiplication. The FPGA parallel architecture, ping-pong cache and fixed-point number
processing are adopted,
microsecond-level low-
delay recovery is achieved, hardware resource occupation is greatly reduced, robustness in a severe network environment is improved, and the method is suitable for a high-precision
clock synchronization scene of an industrial TSN node.