38results about How to "Minimize latency" patented technology

Provided are a method for allocating a temporary radio network temporary identifier to a terminal within a random access procedure in a wireless communication system, and an apparatus supporting the same. The method for allocating a temporary radio network temporary identifier (T-RNTI) to a user equipment (UE) within a random access procedure in a wireless communication system, includes transmitting, by the UE, a random access preamble to a base station (BS), transmitting, by the UE, a radio resource control (RRC) request message to the BS through a contention-based physical uplink shared channel (PUSCH) resource block in which uplink data can be transmitted without uplink resource allocation scheduling, and receiving, by the UE, an RRC connection setup message identified by a T-RNTI allocated to the UE in response to the RRC request message, wherein the T-RNTI is allocated on the basis of the contention-based PUSCH resource block in which the RRC request message has been transmitted.

A method for simulating the entire superset of potential valid keyword regular expression requests constructed during an Internet browser search and converting the result sets into Environmental Bitmap data to enable efficient and accurate searching without requiring Browser Engine supercomputer cluster searching capabilities.

A method for transmitting a stream of data over a channel made up of a plurality of subchannels having respective subchannel rates. The method includes partitioning the data among the subchannels, such that successive words of the data are mapped to the subchannels in alternation responsive to the respective subchannel rates. The words of the data are transmitted over the subchannels to which they are mapped, and are then received and processed to recover the stream of data.

A latency reduction method for read operations of an array of N disk storage devices (210) having n disk storage devices (210A-210H) for data storage and p of disk storage devices (210I, 210J) for storing parity data is provided. Utilizing the parity generation engine's (230) fault tolerance of for a loss of valid data from at least two of the N disk storage devices (210A-210J), the integrity of the data is determined when N−1 of the disk storage devices (210A-210J) have completed executing a read command. If the data is determined to be valid, the missing data of the Nth disk storage device is reconstructed and the data transmitted to the requesting processor (10). By that arrangement the time necessary for the Nth disk storage device to complete execution of the read command is saved, thereby improving the performance of memory system (200).

An apparatus using transmitting antenna diversity to combat degradation due to fading in a wireless communication system. At least two symbols of four symbols to be transmitted through four transmitting antennas are rotated by predetermined phase values. An encoder configures four combinations for four input symbols so that a sequence of four symbols can be transmitted once by each transmitting antenna during each time interval. The combinations are transferred to the four transmitting antennas during four time intervals. Before the four input symbols are transmitted to the transmitting antennas, at least two symbols selected from the four input symbols are rotated by predetermined phase values. Therefore, the maximum diversity order can be obtained, a transmission delay time can be reduced, and the effect of fast fading can be reduced.

A method of and system for frequency clocking in a processor core are disclosed. In this system, at least one processor core is provided, and that at least one processor core has a clocking subsystem for generating an analog output clock signal at a variable frequency. Digital frequency control data and an analog signal are both transmitted to that at least one processor core; and that processor core uses the received analog signal and digital frequency control data to set the frequency of the output clock signal of the clocking subsystem. In a preferred implementation, multiple cores are asynchronously clocked and the core frequencies are independently set.

Providing data to portlets can include a step of registering a plurality of portlets to determine a type of data required by the portlets. The registering can establish a portlet context for handling future data requests for the portlets. A type of information associated with one of the portlets can be determined. A data acquisition process can be initialized to obtain the determined type of information from a data source. A data request can be received for data of the determined type from the associated portlet. Data can be acquired from the data source using the initialized process. The data request can be responded to using the acquired data. In one embodiment, the acquisition of data from the source and the updating of the portlets can occur asynchronously, where a cache is used to temporarily store data acquired from the data source that is used to update the portlets.

A system and method are provided for framing messages in a data streams encoded with redundant information for transmission and recovering the messages at a receiver. The transmission method accepts an energy waveform representing N words at a first bit rate, encoded with redundant information, where each word includes P number of bits. The N words are transformed, creating N transcoded words, where each transcoded word includes Q number of bits, and where Q<P. The N transcoded words are mapped into M lanes in a buffer memory, where M>1 and each lane receives a frame of N / M transcoded words. A frame alignment marker is generated and mapped into each frame. Each frame is represented as an energy waveform that is transmitted on a corresponding physical lane at the first bit rate divided by M.

The invention involves a system and method implementing a wearable device that employs a flexible printed circuit board (PCB), which includes a temperature sensor. The PCB may be printed on a flexible substrate that may be folded to form multiple layers configured to house the sensor and an antenna. The sensor may be housed within said layers and situated at a terminal end of a pathway that may be printed on the PCB, wherein the pathway acts as a contact as well as a conduit of heat from the body of the user to the sensor. The antenna may be housed within the layers of the flexible PCB in a manner such that proper signal transmission is preserved and latency is minimized. Temperature readings may be wirelessly communicated to one or more client devices, which implement one or more algorithms suitable for generating insights regarding health aspects of the user.

Methods, systems, and media are disclosed for autonomic system tuning of simultaneous multithreading (“SMT”). In one embodiment, the method for autonomic tuning of at least one SMT setting for an optimized processing, such as via throughput, latency, and power consumption, of a workload on a computer system includes calling, by a kernel, an SMT scheduler having at least one hook into a genetic library. Further, the method includes obtaining, by the SMT scheduler through the at least one hook, genetic data from the genetic library for the optimized processing of the workload. Further still, the method includes tuning, by the SMT scheduler and based on the obtaining, the at least one SMT setting for at least one cpu of the computer system.

A method of calibrating an elastic interface is provided to automatically achieve a minimal cycle delay through the interface. An existing self-alignment interface (i.e. elastic interface) is used to de-skew within a cycle and stage the data to have it arrive on a given, programmed target cycle. However, this target cycle must be calculated in advance and may be larger than it needs to be, causing more latency on the interface. This method is used to determine the earliest target cycle (with or without additional guard-band). This target cycle is used to adjust the interface automatically to achieve this earliest target cycle. The determination of earliest target cycle can be done once, continuously, or using a sample window. The method also can be used for interfaces that have frequency multipliers or phase shifts at its boundaries.

Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

Systems and methods are disclosed for scheduling threads on an asymmetric multiprocessing system having multiple core types. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Metrics for workloads offloaded to co-processors can be tracked and integrated into metrics for the offloading thread group.

A driver circuit (10) for a light emitting diode comprises a first driver circuit (32, 32', 32') for generating a first current output for driving the light emitting diode, wherein the first driver circuit has a control switch for interrupting the supply of the first current output. A second driver circuit (50) is for generating a second current output for driving the light emitting diode, and the second driver circuit also has a control switch for interrupting the supply of the second current output. The overall output of the driver circuit comprises a pulse width modulated output current which alternates between a high current (Ihigh) generated by the first driver circuit and a low current (I|OW) generated by the second driver circuit. By providing separate driver circuits for two different current requirements, the circuits can be optimised for each function. For example the high current value can comprise an LED operation current, and the low current value can comprise a non-zero measurement current.

A control message processing method and a control message processing apparatus using the method on a wireless mesh network are provided where a neighbor solicitation (NS) information is generated by extracting a part or an entire NS message, the NS message having been generated to request a medium access control (MAC) address of a destination node. A modified route request (RREQ) message, including the NS information, is generated to request the MAC address of the destination node and a routing path to the destination node, and is broadcasted.

Provided is a transversal filter, in which delayers and multipliers are connected in series, includes: a first multiplier for multiplying a first tap coefficient set by a tap coefficient register module and an input signal to output a result of multiplication; a first delayer for delaying the value output from the first multiplier by a predetermined time to output the delayed value; a second multiplier for multiplying a second tap coefficient set by the tap coefficient register module and an input signal to output a result of multiplication; a first adder for adding the value output from the delayer situated upstream to the value output from the second multiplier to output a result of addition; a second delayer for delaying the value output from the first adder by a predetermined time to output the delayed value; and a selector for selecting one of the input signal, the value output from the first delayer, and the value output from the second delayer to output the selected one.

A content joint editing method according to an embodiment of the inventive concept may preserve the real-time property of update of edits as much as possible even if the number of editors increases when multiple editors simultaneously edit content. A content editing method can share and edit various contents without calling a separate external application in an online collaboration service. A content sharing method can manage each user's access rights to a content in individual content units in collaboration service that displays a plurality of contents at the same time in the collaboration space for sharing contents among multiple users.

The invention discloses an IP data packet identification method and a gateway, which are designed to solve the problems that the existing IP data packet identification method and the gateway are low in accuracy rate, low in efficiency and large in time delay. The IP data packet identification method comprises the following steps: extracting the front N bytes of data of an IP data packet application layer, and converting the extracted bytes into a frequency domain signal through Fourier transformation to obtain a characteristic string of the frequency domain, and sorting the IP data packets according to the characteristic string by a machine learning algorithm. The gateway in the invention at least comprises an identifying unit which comprises an extracting module, a Fourier transforming module and a sorting module which are connected orderly. The IP data packet identification method and the gateway have the advantages of high accuracy rate, high efficiency and easy implementation.

Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

The invention relates to a method of, and system for, linear speed control for an electric motor, in which a digital to analog converter means is used for converting an 8-bit digital signal to an analog voltage for setting voltage across a motor, a digital state machine means is used for converting the duty cycle of an input signal for output to the digital to analog converter means, and a closed loop feedback loop means is used for monitoring and setting the voltage across the motor. An over-current sense circuit can be used for monitoring the current across the electric motor. An over / under voltage sense circuit can be used for monitoring voltage of the electric motor. The resulting 8-bit digital control signal is converted to an analog voltage for the electric motor. Such methods and systems find particular use in automotive applications.

The invention relates to a method of, and system for, linear speed control for an electric motor, in which a digital to analog converter means is used for converting an 8-bit digital signal to an analog voltage for setting voltage across a motor, a digital state machine means is used for converting the duty cycle of an input signal for output to the digital to analog converter means, and a closed loop feedback loop means is used for monitoring and setting the voltage across the motor. An over-current sense circuit can be used for monitoring the current across the electric motor. An over / under voltage sense circuit can be used for monitoring voltage of the electric motor. The resulting 8-bit digital control signal is converted to an analog voltage for the electric motor. Such methods and systems find particular use in automotive applications.

A remote support system facilitates assignment of vehicles to remote support agents for providing teleoperation or other remote support services. The remote support system may generate assignments based on a mapping function that optimizes various parameters based on sensed data associated with the vehicle, a requested service mode of the vehicle, or other factors. In some situations, the remote support server assigns a redundant set of remote support agents to a vehicle that provide similar command streams. The vehicle selects between the command streams to minimize latency or another performance parameter. Alternatively, the remote support server assigns multiple diverse remote support agents to a vehicle that generate diverse command streams. A proxy agent then generates a consensus command stream for providing to the vehicle.

A control message processing method and a control message processing apparatus using the method on a wireless mesh network are provided where a neighbor solicitation (NS) information is generated by extracting a part or an entire NS message, the NS message having been generated to request a medium access control (MAC) address of a destination node. A modified route request (RREQ) message, including the NS information, is generated to request the MAC address of the destination node and a routing path to the destination node, and is broadcasted.

The invention discloses a request handling method of a 3D MLC flash device. The method comprises the following steps: performing a read request by a read request fir mode; performing a write request while a wafer is idle; ensuring that the working mode of the related wafer is consistent with the working mode of the related block during performing the read / write request; performing trash recoveryrequest while the wafer is idle; selecting the block with the least active pages in the block under an SLC mode as the block to be recovered in case of insufficient current capacity of the device; selecting an idle block of the SLC mode as a target block in case of jam in current array of the device; setting the wiped working mode of the block to be recovered as the MLC mode in case of insufficient current capacity of the device; and circularly setting the working mode of the next wafer as the SLC mode in case that the total wiping quantity of all wafers is certainly increased. According to the method, the new properties of a 3D MLC flash chip can be fully utilized, so that the delay time in trash recovery can be decreased, and the service life of the flash device is prolonged.

An apparatus for traffic security processing in a slicing service of mobile edge computing according to an embodiment of the present invention includes: a plurality of security modules for analyzing a received packet to respectively execute security functions suitable for slicing security of mobile edge computing; a controller for managing a slicing security module list in the mobile edge computing; and a main security module for analyzing a received packet on the basis of the slicing security module list to determine a security function to be executed and priority of the security function to be executed, wherein the controller transmits the received packet to at least one corresponding security module among the plurality of security modules according to the priority of the security function to be executed, which is determined by the main security module.

Certain embodiments relate to a method for use in a wireless device. The method includes allocating uplink power between parallel transmissions during subframes that the wireless device has scheduled on two or more uplink physical channels. The parallel transmissions include one or more short transmission time interval sTTI transmissions, and the UL power is allocated according to at least one prioritization rule. According to one of said prioritization rules, sTTI transmissions comprising control information are prioritized over sTTI transmissions comprising data but without any control information. According to another of the prioritization rules, transmissions with shorter transmission time intervals are prioritized over transmissions with longer transmission time intervals.

A content joint editing method according to an embodiment of the inventive concept may preserve the real-time property of update of edits as much as possible even if the number of editors increases when multiple editors simultaneously edit content. A content editing method can share and edit various contents without calling a separate external application in an online collaboration service. A content sharing method can manage each user's access rights to a content in individual content units in collaboration service that displays a plurality of contents at the same time in the collaboration space for sharing contents among multiple users.