38 results about "Ramp time" patented technology

System, device and method for providing neuromuscular electrical stimulation (NMES) to muscles of foot. The device includes an electrical signal generator for producing a wave pattern of variable frequency, duration, intensity, ramp time and on-off cycle. The device further includes surface electrodes for being positioned over the foot muscles or around ankles and attached to the signal generator. The device includes a wearable device for positioning a first electrode adjacent a heel of the wearer's foot and a second electrode adjacent an arch of the foot. The signal generator is programmed to stimulate the foot muscles and nerves. Location of the electrodes and the programming are adjusted to reduce pooling of the blood in the soleal veins of the calf and enhance venous blood flow to prevent deep vein thrombosis (DVT); to enhance venous blood flow for the post-thrombotic syndrome patient; to expedite wound healing; to reduce neuropathic pain of the foot and ankle, chronic musculoskeletal pain of the ankle and foot, and acute post-operative foot and ankle pain; and to prevent muscular atrophy of the foot muscles.

The present invention relates to the domain of video equipment. It concerns more specifically a transmission device able to transmit packets, said device comprising the means to extract image ticks from a synchronisation signal, the means to initialise an image counter from said image ticks, the means to initialise a CPT_ PCR counter every 'm' passage through zero of the image counter, CPT_PCR producing counting ramps CSE_PCR with a range M, the means to sample the counting ramps CSE_PCR every Tech period, where Tech is from a time base synchronised on all the stations of said network, and the means to transmit packets comprising a PCRe sample of the CSE_PCR counting ramp. According to the invention, it also comprises the means to insert in the packet: - an Num index identifying the CSE_PCR counting ramp from which the PCRe sample is realised, and - a time label Datejnit indicating a CSE_PCR counting ramp timestamp passage through a reference value PCR_REF comprised between 0 and M-1.

The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the effective intrinsic jitter, and reduce the measurement time. Improved aspects of the present subject matter correspond to the introduction of a current mirror for improved settling time, a high frequency clock for improved resolution and ADC sample processing to improve resolution and accuracy.

The present invention relates to a method of interconnection routing for preventing crosstalk. The method comprises the following steps. Providing an aggressor connection path as a first net. Providing a victim connection path according to the requirements of a second net. Determining a voltage ramp time of the aggressor connection path, a victim total length of the victim connection path, a coupled wire length between the aggressor connection path and the victim connection path, and an equivalent load corresponding to the victim connection path. Evaluating a noise metric according to the voltage ramp time, the victim total length, the coupled wire length and the equivalent load. Modifying the victim connection path to shorten the coupled wire length if the noise metric is greater than a pre-determined value. Finally designating the victim connection path as the second net if the noise metric is less than the pre-determined value.

A method is provided for performing continuous single insertion semiconductor testing of a group of semiconductors that are divided into a first subgroup and a second subgroup at multiple different temperatures. The single insertion semiconductor testing is performed by sequentially executing testing cycles, characterized by the tester alternately executing temperature testing periods and temperature ramping periods for the first subgroup, while simultaneously executing temperature ramping periods and temperature testing periods for the second subgroup. The temperature testing periods operate at two or more different temperatures. The single insertion testing sequence entirely eliminates tester index time when the testing time is equal to or greater than the ramping times, and substantially reduces tester index time when the testing time is less that the ramping times.