The invention provides a universal calibration method for transmission
path delay errors of a parallel ADC sampling
system, and aims to provide a universal method capable of adapting to sampling frequency changes and correcting multichannel
data input delay. According to the technical scheme, a
clock and a
signal are configured into multi-channel output through an AD
chip integrated with M channels, and an AD is connected with an FPGA through a serial
peripheral interface to form a high-speed variable sampling rate
system. The AD performs multi-channel parallel sampling on high-speed signals to realize first-stage
speed reduction, and the FPGA performs serial-parallel conversion by adopting serial-parallel conversion primitives or serial-parallel conversion IP cores to realize second-stagespeed reduction. After the FPGA configures an AD to send a
test sequence, a calibration instruction and a state
machine are started, a time
delay parameter
calibration algorithm is operated, time
delay parameters are dynamically placed into an FPGA input time delay control primitive, all
data lines in channels and among the channels are aligned, the AD exits from the
test sequence to output actual signals, and
system input time delay calibration is completed.