The present invention provides a method for balancing timing, providing a design
layout, the design
layout includes multiple design modules, each design module includes multiple ports; defining the design modules that need to be timing balanced; formulating design rules for timing balance, including placing the defined design modules relatively parallel at a
set distance, so that when the ports between the defined design modules are connected, the
bus length of the connection is the shortest; resetting the positions of multiple design modules according to the design rules, and connecting the ports between the design modules. The method of the present invention finds out the modules related to the address and data, places the units related to the timing balance close to each other, ensures that the
bus connection is balanced and the routing is short, and in the redesigned
layout, the data register corresponds to the memory port, and the
bus connection is balanced and short.