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36results about How to "Unnecessary power consumption" patented technology

Indication and processing method and device for resource occupancy mode

There is disclosed a method of indicating a resource occupancy scheme and processing a resource occupancy scheme indicator so as to enable a UE to be aware a resource occupancy scheme of the network side and avoid an unnecessary power waste and unnecessary interference, and in the method, a base station generates a corresponding resource indicator for a resource occupancy scheme of a legacy control resource area and an enhanced control resource area in each downlink subframe to be transmitted in a specific periodicity and sends the resource indicator to a UE in a resource indication message, and the UE determines from the obtained resource indicator the resource occupancy scheme of the legacy control resource area and the enhanced control resource area in each downlink subframe to be transmitted in the specific periodicity and performs a corresponding resource handling mode, so that the UE can blindly detect in PDCCH common and user spaces or receive control information carried on PHICH resource at an accurate position to thereby avoid an unnecessary power waste of and unnecessary interference to the UE due to blind detection or reception and improve effectively the performance of a system.
Owner:DATANG MOBILE COMM EQUIP CO LTD

Control of clock gating

Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal. It comprises: an input for receiving mode switching signals indicating said synchronous circuitry is to switch between modes, said mode switching signals comprising a clock gating request signal indicating said synchronous circuitry is to enter a sleep mode during which said circuitry is not clocked and a wake up request signal indicating said synchronous circuitry is to enter an operational mode during which said circuitry is clocked; and is responsive to said clock gating request signal to gate said clock signal such that no clock signal is output to said synchronous circuitry and being responsive to said wake up request signal to output said clock signal to said synchronous circuitry. The clock signal control circuitry further comprises: a data store for storing a delay value; and delay circuitry for delaying switching of said clock signal between modes in response to at least one of said mode switching signals, said delay circuitry delaying said switching by an amount dependent upon said stored delay value.
Owner:ARM LTD
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