134 results about "Binade" patented technology

Systems, methods, and software can be used to generate natural language description of a software code. In some aspects, a method includes: processing a binary code by using a file encoder model to obtain a file embedding vector; and processing the file embedding vector to obtain a text description of the binary code by using a large language model (LLM).

The invention belongs to the field of computers, and discloses a variable-precision parallelization index floating point number storage and calculation integrated method based on an FPGA (Field Programmable Gate Array), which specifically comprises the following steps of: inputting decimal floating point data; an index floating-point number binary sequence format is defined, decimal floating-point data values are converted into the index floating-point number binary sequence format, parameters of the index floating-point number binary sequence format comprise sign bits, index bits, mantissa bits, specified index offset and mantissa bit width, and the mantissa bit width is dynamically adjusted according to calculation requirements; based on decimal floating point data numerical values, extracting parameters of an index floating point number binary sequence, and storing the parameters in a register of the FPGA as operands; performing displacement sorting on the two operands stored in the register, and calculating an absolute value of a difference between exponent bits and a difference between mantissa bits of the two operands; the problems that in the prior art, a floating-point number storage scheme is low in calculation efficiency and insufficient in precision in an application scene where the dynamic range changes drastically are solved.

The invention provides a large model assisted Fuzz test Harness generation method and system, and the method comprises the steps: migrating a library of a QNX platform to a Linux environment for operation, and carrying out the glue code packaging of interface difference and system call difference through the generality that the library of the QNX platform and the Linux environment share a POSIX standard, thereby achieving the automatic adaptation of key API and context constraint; then analyzing binary semantics by means of an intelligent Agent constructed by a large model, automatically generating a Harness skeleton, focusing potential dangerous points (such as memory management, character string processing functions and the like), generating an initial seed in combination with a static or dynamic analysis result, and finally executing a Fuzz test in a controllable execution environment. And high coverage and rapid vulnerability positioning of the multi-dimensional attack vector of the target library are realized. The technical problems that Harness writing highly depends on expert experience, a customized generation strategy for target binary semantics is lacked, and comprehensive understanding on the binary semantics and context constraints is lacked are solved.

Methods, computer program products, and systems are presented. The method computer program products, and systems can include, for instance: performing static analysis of program source code defining a computer program, wherein the computer program comprises a pointer operation callee and at least one caller that can pass a pointer parameter to the pointer operation callee; generating, in dependence on the static analysis of program source code, binary code executable so that the pointer operation callee, in runtime, performs a runtime check for determining pointer alias status of the pointer operation callee; and generating, in dependence on the static analysis of program source code, executable binary code executable so that the pointer operation callee, in runtime, performs selecting and activating an executable code path in dependence on a result of the runtime check.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a random noise value for use in providing differential privacy in multiparty computation. One of the method includes receiving, by a first party participating in a multiparty secure computation (“MPC”) instance, a share of a first n-bit random binary number and a plurality of function table segments; generating a share of a second n-bit random binary number; calculating a first value based on a comparison between the share of the first and second n-bit random binary numbers; reconstructs an overall value of a comparison between the first and second n-bit random binary numbers; and determining a share of the random noise value based on the overall value and the plurality of function table segments.

The invention discloses a multi-operand carry lookahead parallel addition processing method, which comprises the following steps of: firstly, performing column addition operation, taking the same-power bits of each addend as operands, obtaining an accumulation part, BP [i] and an accumulation carry value BG [i] according to a specific logic equation, fixing the digit of the BP [i], enabling the digit of the BG [i] and the number of the operands to be in a logarithmic relationship, and realizing carry (pre-) compression. Then, a multi-bit carry advance algorithm is adopted, multi-bit carry advance budgeting is carried out through a recursive expression on the basis of the binary system principle, and the efficiency bottleneck of multi-operand additive operation is broken through; the method has wide application prospects in the fields of signal processing, automatic control, artificial intelligence, high-performance calculation and the like.

A computing system can obtain a machine-learned model comprising one or more parameters having a four-bit binary format. The four-bit binary format can correlate a plurality of sixteen respective binary values to a plurality of sixteen corresponding numerical values represented by the binary values. The sixteen numerical values can be symmetric about a median. A plurality of step sizes between the sixteen numerical values can be non-uniform. The computing system can obtain one or more input values for one or more layers of the machine-learned model. The computing system can process, based at least in part on the one or more parameters having the four-bit binary format, the one or more input values to generate one or more output values.

The invention belongs to the technical field of product ID generation, and discloses a PnP-compatible unique EDID dynamic generation method and device, and the method comprises the steps: calculating a first binary length of a first character string; if yes, performing filling operation on the binary bit of the first character string to obtain a target character string with the binary bit of 512; expanding the 32-bit words of the first number block to obtain 32-bit words of a second number block, and performing cyclic compression of a second number round on the 32-bit words of the second number block to obtain binary variable values of the first number bits; and carrying out interception and modulo 216 operation on a binary variable value of a specified interval span in the binary variable values of the first number bits, and embedding a corresponding field of the original EDID to obtain a unique EDID of the product equipment. It is ensured that the PnPID in the EDID is globally unique, matching and installation of the corresponding drive are accurately triggered, and manual equipment distinguishing depending on a user is reduced; and the compatibility hidden danger caused by the drive matching problem when the equipment is accessed to the operating system supporting the PnP is also avoided.

This invention belongs to the field of power grid fault diagnosis technology and discloses a power grid fault diagnosis method and system based on differential evolutionary logic operations. The method includes: collecting the action information of protection devices and circuit breakers in the power system; filtering out a set of candidate elements that have experienced faults based on preset association rules between faulty elements and protection / circuit breaker actions; establishing a 0-1 integer programming model based on the determined protection action information, circuit breaker action information, and candidate element set; and solving the 0-1 integer programming model using an improved differential evolutionary algorithm based on logic operations to determine the fault state of the candidate elements. This invention directly encodes individuals using binary, eliminating the need for floating-point to binary conversion. It also constructs a binary mutation operator and an improved crossover operator based on logic operations and employs adaptive parameter adjustment to balance the population diversity and search efficiency of the algorithm.

Systems, methods, and software can be used to detect backdoors in binary software code. In some aspects, a method comprises: obtaining, by a server, binary software code corresponding to source code; generating, by the server, a backdoor abstraction of the binary software code; and generating, by the server, a backdoor risk assessment based on the backdoor abstraction of the binary software code.

State of the art code matching approaches have the disadvantage that they rely on the line numbers provided by source code and binary parsers to establish mapping and do not work since changes introduced by compiler may be much more complex. Some approaches do not work as the source code of application and its binary version may not share the vocabulary. Machine learning based techniques have the disadvantage that they require significant amount of training data, which may not be available in abundance. Method and system disclosed herein provide a mechanism matching score for each of a plurality of code fragments in the intermediate representation of the source code file for each of a plurality of binary fragments in the intermediate representation of the binary file.

The invention discloses a cross-ISA (Industrial Standard Architecture) extension program translation method based on binary rewriting, which comprises the following steps of: 1) naming an instruction set ISA of a program to be translated as an original ISA, and naming an instruction set ISA on target hardware for running original ISA extension as a target ISA; 2) performing comparative analysis on a binary file corresponding to the original ISA extension compilation and a binary file corresponding to the target ISA extension compilation to obtain an instruction needing to be translated relative to the target ISA extension in the original ISA extension, and segmenting the instruction into a plurality of program basic blocks needing to be translated; 3) allocating a jump instruction and an address space for translating and storing translated codes to each program basic block; (4) distributing the program basic blocks into the corresponding address spaces through a jump instruction to carry out static binary translation, and generating a static file; and (5) distributing a loading address for the static file by utilizing a loader according to the address distribution information in the static file, and loading the static file to a corresponding position.

The present invention discloses a data serialization method, a deserialization method, and an inter-process instruction parameter passing method. For each instruction number and its corresponding instruction parameter type, the mapping relationship is written in a configuration file, and the structure information of the instruction parameter type is written. Then, the configuration file is compiled into a binary obj configuration file. In subsequent serialization and deserialization, the instruction parameter type corresponding to the instruction number is found through this obj configuration file, and for the instruction parameter, each field is serialized and deserialized according to the preset serialization method and deserialization method inherent in its field type based on its field composition. It achieves automated processing of instruction data of all instruction parameter types, converts the existing manual hard-coding method into a method of leading and processing data through a configuration file, improves programming and execution efficiency, is easy to understand and maintain, has high accuracy, and good effects.

The invention provides a floating point unit exception handling method and device of an industrial safety operating system and a medium. The method comprises the following steps: hooking a floating point exception handling function at an undefined instruction exception entry, and enabling the exception of a floating point unit to enter a unified handling flow; reading an abnormal comprehensive register of the processor to identify the floating point operation exception type, and reading a program counter register to obtain a trigger instruction address; performing standardized calculation on the operation under abnormal conditions according to a binary floating point arithmetic standard, generating result data corresponding to the operation, and forming abnormal mark information; writing the result data back to the destination register, and calculating a next instruction address according to the instruction set rule; and outputting the trigger instruction address, the exception type, the source operand and the result data as exception information through an interface from the kernel to a user side. According to the method, instant processing of the abnormal trigger point, continuous execution of the instruction, real-time output of the abnormal context and reduction of positioning and recovery time delay can be realized.

This invention discloses a method for collecting evidence from control logic attacks on industrial controllers. The method primarily involves extracting PLC binary control application files by simulating the PLC's upload function; performing reverse engineering on the extracted binary files, including identifying the PLC binary's assembly instruction set architecture, performing disassembly analysis, identifying the PLC programming language, and generating an assembly log file; and performing attack detection, attack location, attack analysis, and attack recovery based on the generated assembly log file. This method effectively collects evidence from control logic attacks on industrial controllers without requiring PLC source code, plant behavior models, or any network traffic. The method can automatically execute the entire process within acceptable time and memory overhead.

The invention relates to the field of intelligent analysis, and particularly discloses a binary code-oriented static taint analysis system and method, which introduces an on-demand micro-symbol execution mechanism on the basis of basic data flow analysis through binary lifting and control flow diagram construction, that is, aiming at memory ambiguous nodes in a data dependence diagram, a micro-symbol execution mechanism is introduced on the basis of the basic data flow analysis; refined alias analysis is achieved through reverse instruction slicing and constraint solution, then an enhanced data dependency graph is generated, and path-sensitive taint propagation iteration is conducted on the basis to generate a final taint state table. In this way, complex dynamic memory addressing can be effectively recognized, taint chain breakage and misinformation explosion caused by ambiguity ignoring or excessive approximation are avoided, and resource allocation of an analysis engine is remarkably optimized.

The invention relates to the technical field of network security and software reverse engineering, and discloses a binary function symbol recovery method based on LLM fusion interprocess context. The method comprises the following steps: firstly, extracting multi-dimensional feature information from a target binary function, wherein the multi-dimensional feature information comprises a function body pseudo code, a call point context code snippet, call chain information and a character string parameter transmitted by a call point; then, the multi-dimensional information is structured and constructed into prompts, the prompts are input into a large language model which is finely adjusted by a specific task for reasoning, and finally candidate function names are generated. The invention further discloses an LLM fine tuning technology fusing the multi-dimensional context information. According to the LLM fine tuning technology, efficient parameter fine tuning is carried out on the basic model by constructing a training sample set containing a function body, a calling context and character string parameters. According to the method, the inter-process context information is systematically introduced, so that the accuracy and semantic fitness of binary function symbol recovery are remarkably improved.

The embodiment of the invention relates to the field of de-obfuscation, in particular to an ARM binary code de-obfuscation method and device based on a large language model. A specific embodiment of the method comprises the steps of performing ARM disassembly processing on acquired target code information to generate initial disassembly code information; performing data cleaning processing on the initial disassembly code information to generate assembly code information; inputting the assembly code information into a confusion detection model included in a pre-trained LLM-DAS model to obtain confusion information; and in response to determining that the obfuscation information meets the preset obfuscation condition, inputting the obfuscation information and the assembly code information into a de-obfuscation model included in a pre-trained LLM-DAS model to obtain de-obfuscation code information. According to the embodiment, the potential of the large language model in the de-obfuscation field can be fully mined, and the de-obfuscation effect of the ARM binary code is improved.

There are provided systems and methods for reducing quantization errors, including method of optimizing a routine for a hardware-based processing system having a fixed length two's complement binary representation, the method comprising: receiving an instruction sequence arranged to perform the routine, wherein the instruction sequence comprises a set of arithmetic operations, wherein the outputs of the arithmetic operations exceed a precision of the hardware-based processing system; identifying one or more pairs of sub-sets of instructions in the sequence of instructions, the sub-sets of each pair having a respective comparable truncation error; and generating an optimized routine by modifying one of the sub-sets of each pair to invert the sign of one or more inputs to said sub-sets and modifying the instruction sequence to compensate for the said inversion.

The invention provides a central binomial distribution random number sampling system and method. The system comprises an accumulation module, an extension module and an addition module, the accumulation module is configured to obtain a preset number of random numbers at the front end of the binary sequence and accumulate the random numbers to generate a first accumulation result; obtaining a preset number of random numbers at the rear end of the binary sequence and accumulating the random numbers to generate a second accumulation result; the binary sequence is composed of a numerical value 0 and a numerical value 1; the expansion module is configured to expand the first accumulation result by one sign bit 0 to obtain a first complement; performing negation and 1 addition operation on the second accumulation result, and expanding one sign bit 1 to obtain a second complement; the addition module is configured to obtain a target random number according to the first complement and the second complement; the target random number accords with the central binomial distribution, so as to solve the problems of low calculation speed, high power consumption and high delay of the sampling work of the central binomial distribution random number by the current universal calculation platform.

This invention relates to a decomposition circuit (UPCK) for an input binary number in a binary arithmetic unit, the input number having an FP32 floating-point format, the decomposition circuit being hardwired to: decompose the input number ( X Decomposed into high and low component pairs with an internal format having a 9-bit exponent and 12-bit significant digits. Xh,Xl ); the significant number of the high component ( Hmm The bits of the input number are directly connected to the circuit that provides the value of the implicit bits and the most significant bit of the fractional mantissa; the significant bits of the lower components ( Xlm The bits of the input number are directly connected to the remaining bits of the decimal part; the input number ( X The index plus 12 is assigned to the index with the higher component () Loxhë ); and the input number ( X The unchanged index is assigned to the index with the lower component () Xle ).

The invention discloses a DSP architecture-oriented worst run time program analysis method and system, and belongs to the technical field of binary program static analysis. The method comprises the following steps: generating a control flow diagram of a target program; according to the control flow diagram, an LASW loop structure in a target program is extracted, and the upper bound of the minimum number of cycles of the LASW loop structure is calculated; and based on the control flow diagram and the minimum cycle index upper bound, carrying out worst running time analysis on the target program to obtain a worst running time analysis result of the target program. According to the method, the accuracy and the automation degree of worst running time analysis can be improved.

A method used when adding two numbers in the form of binary strings, which makes a given bit position in one of the binary strings available to store a carry-over value. The method comprises the steps

Disclosed is saturation logic system 100 for adding a pair of binary numbers. The logic circuit receives first and second inputs 110, comprising respective first and second numbers of bits, the secon

This invention relates to a method and system for decompiling optimized code based on deep learning. The method includes the following steps: obtaining a low-level intermediate language (LIR) and a high-level intermediate language (HIR) using a low-level programming language (LPL) and a high-level programming language (HPL) as training datasets; training a deep learning model using the training datasets to learn the mapping rules between LIRs and HIRs; using the trained deep learning model to translate the LIR of the LPL to be decompiled into the HIR; performing data flow recovery and control structure recovery on the HIR obtained by the deep learning model to generate HPL code; and using a similarity matching algorithm to find source code similar to the generated HPL code, transferring the semantic information from the source code to the generated HPL code. This invention can automatically convert LPL to HPL and has high accuracy for both optimized and non-optimized binary decompilation.

According to the signaling analysis method based on control plane protocol transmission, an ASN.1 coding rule is adopted in a control plane protocol, and the method comprises the steps that at least one hidden signaling domain used for indicating the length of a data boundary is extracted from coded binary signaling data; positioning to the target cell based on the identification information of the target cell; based on the length information extracted from the hidden signaling domain, determining the offset and length of the target cell relative to the signaling initial position in the binary signaling data; and calling an analytic function to analyze the target cell based on the shift amount and the length. According to the method, the data processing delay can be reduced, and the cell extraction flexibility and response speed are improved.

An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, for each coefficient of a plurality of coefficients included in a block, determines a base level relating to Context-Based Adaptive Binary Arithmetic Coding (CABAC) for the coefficient, and encodes an absolute value of the coefficient. In determining the base level, when one or more flags are used in encoding the absolute value of the coefficient, the base level is determined to be a first value, and when one or more flags are not used in the encoding, the base level is determined to be a second value that is smaller than the first value. In encoding the absolute value of the coefficient, when one or more flags are not used, a rice parameter is determined based on the base level which is equal to the second value, and the coefficient is binarized using the rice parameter.

Various embodiments provide a system, method, and device for generating a signature for Windows .NET binaries. The method incudes (i) generate a file signature based on code using a hashing technique, and (ii) classify a sample using the file signature based on the code.

To encode with CABAC, a non-binary syntax element value is mapped to a binary sequence (bin string), through a binarization process. A binary arithmetic coding engine encodes or decodes a bin, in a regular (context-based) mode and a bypass mode.