97 results about "Binade" patented technology

The invention provides a large model assisted Fuzz test Harness generation method and system, and the method comprises the steps: migrating a library of a QNX platform to a Linux environment for operation, and carrying out the glue code packaging of interface difference and system call difference through the generality that the library of the QNX platform and the Linux environment share a POSIX standard, thereby achieving the automatic adaptation of key API and context constraint; then analyzing binary semantics by means of an intelligent Agent constructed by a large model, automatically generating a Harness skeleton, focusing potential dangerous points (such as memory management, character string processing functions and the like), generating an initial seed in combination with a static or dynamic analysis result, and finally executing a Fuzz test in a controllable execution environment. And high coverage and rapid vulnerability positioning of the multi-dimensional attack vector of the target library are realized. The technical problems that Harness writing highly depends on expert experience, a customized generation strategy for target binary semantics is lacked, and comprehensive understanding on the binary semantics and context constraints is lacked are solved.

A computing system can obtain a machine-learned model comprising one or more parameters having a four-bit binary format. The four-bit binary format can correlate a plurality of sixteen respective binary values to a plurality of sixteen corresponding numerical values represented by the binary values. The sixteen numerical values can be symmetric about a median. A plurality of step sizes between the sixteen numerical values can be non-uniform. The computing system can obtain one or more input values for one or more layers of the machine-learned model. The computing system can process, based at least in part on the one or more parameters having the four-bit binary format, the one or more input values to generate one or more output values.

The invention belongs to the technical field of product ID generation, and discloses a PnP-compatible unique EDID dynamic generation method and device, and the method comprises the steps: calculating a first binary length of a first character string; if yes, performing filling operation on the binary bit of the first character string to obtain a target character string with the binary bit of 512; expanding the 32-bit words of the first number block to obtain 32-bit words of a second number block, and performing cyclic compression of a second number round on the 32-bit words of the second number block to obtain binary variable values of the first number bits; and carrying out interception and modulo 216 operation on a binary variable value of a specified interval span in the binary variable values of the first number bits, and embedding a corresponding field of the original EDID to obtain a unique EDID of the product equipment. It is ensured that the PnPID in the EDID is globally unique, matching and installation of the corresponding drive are accurately triggered, and manual equipment distinguishing depending on a user is reduced; and the compatibility hidden danger caused by the drive matching problem when the equipment is accessed to the operating system supporting the PnP is also avoided.

This invention belongs to the field of power grid fault diagnosis technology and discloses a power grid fault diagnosis method and system based on differential evolutionary logic operations. The method includes: collecting the action information of protection devices and circuit breakers in the power system; filtering out a set of candidate elements that have experienced faults based on preset association rules between faulty elements and protection / circuit breaker actions; establishing a 0-1 integer programming model based on the determined protection action information, circuit breaker action information, and candidate element set; and solving the 0-1 integer programming model using an improved differential evolutionary algorithm based on logic operations to determine the fault state of the candidate elements. This invention directly encodes individuals using binary, eliminating the need for floating-point to binary conversion. It also constructs a binary mutation operator and an improved crossover operator based on logic operations and employs adaptive parameter adjustment to balance the population diversity and search efficiency of the algorithm.

Systems, methods, and software can be used to detect backdoors in binary software code. In some aspects, a method comprises: obtaining, by a server, binary software code corresponding to source code; generating, by the server, a backdoor abstraction of the binary software code; and generating, by the server, a backdoor risk assessment based on the backdoor abstraction of the binary software code.

State of the art code matching approaches have the disadvantage that they rely on the line numbers provided by source code and binary parsers to establish mapping and do not work since changes introduced by compiler may be much more complex. Some approaches do not work as the source code of application and its binary version may not share the vocabulary. Machine learning based techniques have the disadvantage that they require significant amount of training data, which may not be available in abundance. Method and system disclosed herein provide a mechanism matching score for each of a plurality of code fragments in the intermediate representation of the source code file for each of a plurality of binary fragments in the intermediate representation of the binary file.

The invention discloses a cross-ISA (Industrial Standard Architecture) extension program translation method based on binary rewriting, which comprises the following steps of: 1) naming an instruction set ISA of a program to be translated as an original ISA, and naming an instruction set ISA on target hardware for running original ISA extension as a target ISA; 2) performing comparative analysis on a binary file corresponding to the original ISA extension compilation and a binary file corresponding to the target ISA extension compilation to obtain an instruction needing to be translated relative to the target ISA extension in the original ISA extension, and segmenting the instruction into a plurality of program basic blocks needing to be translated; 3) allocating a jump instruction and an address space for translating and storing translated codes to each program basic block; (4) distributing the program basic blocks into the corresponding address spaces through a jump instruction to carry out static binary translation, and generating a static file; and (5) distributing a loading address for the static file by utilizing a loader according to the address distribution information in the static file, and loading the static file to a corresponding position.

The invention provides a floating point unit exception handling method and device of an industrial safety operating system and a medium. The method comprises the following steps: hooking a floating point exception handling function at an undefined instruction exception entry, and enabling the exception of a floating point unit to enter a unified handling flow; reading an abnormal comprehensive register of the processor to identify the floating point operation exception type, and reading a program counter register to obtain a trigger instruction address; performing standardized calculation on the operation under abnormal conditions according to a binary floating point arithmetic standard, generating result data corresponding to the operation, and forming abnormal mark information; writing the result data back to the destination register, and calculating a next instruction address according to the instruction set rule; and outputting the trigger instruction address, the exception type, the source operand and the result data as exception information through an interface from the kernel to a user side. According to the method, instant processing of the abnormal trigger point, continuous execution of the instruction, real-time output of the abnormal context and reduction of positioning and recovery time delay can be realized.

The invention relates to the field of intelligent analysis, and particularly discloses a binary code-oriented static taint analysis system and method, which introduces an on-demand micro-symbol execution mechanism on the basis of basic data flow analysis through binary lifting and control flow diagram construction, that is, aiming at memory ambiguous nodes in a data dependence diagram, a micro-symbol execution mechanism is introduced on the basis of the basic data flow analysis; refined alias analysis is achieved through reverse instruction slicing and constraint solution, then an enhanced data dependency graph is generated, and path-sensitive taint propagation iteration is conducted on the basis to generate a final taint state table. In this way, complex dynamic memory addressing can be effectively recognized, taint chain breakage and misinformation explosion caused by ambiguity ignoring or excessive approximation are avoided, and resource allocation of an analysis engine is remarkably optimized.

The invention relates to the technical field of network security and software reverse engineering, and discloses a binary function symbol recovery method based on LLM fusion interprocess context. The method comprises the following steps: firstly, extracting multi-dimensional feature information from a target binary function, wherein the multi-dimensional feature information comprises a function body pseudo code, a call point context code snippet, call chain information and a character string parameter transmitted by a call point; then, the multi-dimensional information is structured and constructed into prompts, the prompts are input into a large language model which is finely adjusted by a specific task for reasoning, and finally candidate function names are generated. The invention further discloses an LLM fine tuning technology fusing the multi-dimensional context information. According to the LLM fine tuning technology, efficient parameter fine tuning is carried out on the basic model by constructing a training sample set containing a function body, a calling context and character string parameters. According to the method, the inter-process context information is systematically introduced, so that the accuracy and semantic fitness of binary function symbol recovery are remarkably improved.

The embodiment of the invention relates to the field of de-obfuscation, in particular to an ARM binary code de-obfuscation method and device based on a large language model. A specific embodiment of the method comprises the steps of performing ARM disassembly processing on acquired target code information to generate initial disassembly code information; performing data cleaning processing on the initial disassembly code information to generate assembly code information; inputting the assembly code information into a confusion detection model included in a pre-trained LLM-DAS model to obtain confusion information; and in response to determining that the obfuscation information meets the preset obfuscation condition, inputting the obfuscation information and the assembly code information into a de-obfuscation model included in a pre-trained LLM-DAS model to obtain de-obfuscation code information. According to the embodiment, the potential of the large language model in the de-obfuscation field can be fully mined, and the de-obfuscation effect of the ARM binary code is improved.

There are provided systems and methods for reducing quantization errors, including method of optimizing a routine for a hardware-based processing system having a fixed length two's complement binary representation, the method comprising: receiving an instruction sequence arranged to perform the routine, wherein the instruction sequence comprises a set of arithmetic operations, wherein the outputs of the arithmetic operations exceed a precision of the hardware-based processing system; identifying one or more pairs of sub-sets of instructions in the sequence of instructions, the sub-sets of each pair having a respective comparable truncation error; and generating an optimized routine by modifying one of the sub-sets of each pair to invert the sign of one or more inputs to said sub-sets and modifying the instruction sequence to compensate for the said inversion.

This invention relates to a decomposition circuit (UPCK) for an input binary number in a binary arithmetic unit, the input number having an FP32 floating-point format, the decomposition circuit being hardwired to: decompose the input number ( X Decomposed into high and low component pairs with an internal format having a 9-bit exponent and 12-bit significant digits. Xh,Xl ); the significant number of the high component ( Hmm The bits of the input number are directly connected to the circuit that provides the value of the implicit bits and the most significant bit of the fractional mantissa; the significant bits of the lower components ( Xlm The bits of the input number are directly connected to the remaining bits of the decimal part; the input number ( X The index plus 12 is assigned to the index with the higher component () Loxhë ); and the input number ( X The unchanged index is assigned to the index with the lower component () Xle ).

A method used when adding two numbers in the form of binary strings, which makes a given bit position in one of the binary strings available to store a carry-over value. The method comprises the steps

Disclosed is saturation logic system 100 for adding a pair of binary numbers. The logic circuit receives first and second inputs 110, comprising respective first and second numbers of bits, the secon

This invention relates to a method and system for decompiling optimized code based on deep learning. The method includes the following steps: obtaining a low-level intermediate language (LIR) and a high-level intermediate language (HIR) using a low-level programming language (LPL) and a high-level programming language (HPL) as training datasets; training a deep learning model using the training datasets to learn the mapping rules between LIRs and HIRs; using the trained deep learning model to translate the LIR of the LPL to be decompiled into the HIR; performing data flow recovery and control structure recovery on the HIR obtained by the deep learning model to generate HPL code; and using a similarity matching algorithm to find source code similar to the generated HPL code, transferring the semantic information from the source code to the generated HPL code. This invention can automatically convert LPL to HPL and has high accuracy for both optimized and non-optimized binary decompilation.

According to the signaling analysis method based on control plane protocol transmission, an ASN.1 coding rule is adopted in a control plane protocol, and the method comprises the steps that at least one hidden signaling domain used for indicating the length of a data boundary is extracted from coded binary signaling data; positioning to the target cell based on the identification information of the target cell; based on the length information extracted from the hidden signaling domain, determining the offset and length of the target cell relative to the signaling initial position in the binary signaling data; and calling an analytic function to analyze the target cell based on the shift amount and the length. According to the method, the data processing delay can be reduced, and the cell extraction flexibility and response speed are improved.

Various embodiments provide a system, method, and device for generating a signature for Windows .NET binaries. The method incudes (i) generate a file signature based on code using a hashing technique, and (ii) classify a sample using the file signature based on the code.

To encode with CABAC, a non-binary syntax element value is mapped to a binary sequence (bin string), through a binarization process. A binary arithmetic coding engine encodes or decodes a bin, in a regular (context-based) mode and a bypass mode.

To provide an optimization system capable of obtaining a high-quality solution rapidly for the mixed binary quadratic programming problem.SOLUTION: An annealing unit performs a first search for an annealing solution using a first solver to reduce the objective function value near a constraint-satisfying solution, and a mixed-integer programming optimization unit performs a second search for a constraint-satisfying solution using a second solver to reduce the linear objective function near the annealing solution obtained by the annealing unit, then by repeatedly executing the first and second searches, the optimal solution is obtained.SELECTED DRAWING: Figure 2

An extensible binary data model compiler is described. A receiver may receive binary specifications, binary data models and / or binary descriptions which are design documents, programming language source files, and / or interface description language definitions that describe, specify and / or model a binary communication protocol, binary data storage format, or binary data processing architecture. A categorizer may distribute binary descriptions to a respective loader, binary specifications to a respective compiler, and / or binary data models to a respective reader. Binary descriptions are normalized and compiled into generic binary models. Binary specifications are compiled into generic binary data models. A reader may read an existing binary data model. A resolver may generate a generic binary data model address for each generic binary data model element within a generic binary data model. A generic binary data model is an independent intermediate representation enabling shared analysis and operations.

A method for testing code coverage of a software program executed by a machine in an industrial system, comprising: obtaining a control flow model of a first version of the software program as a first control flow model; obtaining a control flow model of a second version of the software program as a second control flow model, wherein the second version is a modified version of the first version; comparing the first control flow model with the second control flow model, to identify one or more code changes of the second version compared to the first version; preparing a set of codes to be tested based on the identified one or more code changes; preparing test data for testing the coverage of the set of codes to be tested; compiling the second version into an assembly code or a binary machine code to be executed by a runtime environment of the machine; adding a check point into the assembly code or the binary machine code at a position corresponding to each code in the set of codes to be tested, wherein the check point is an instruction added into the assembly code or the binary machine code that enables the runtime environment to indicate, when the instruction of the check point is executed, that the code in the set of codes to be tested corresponding to the check point is executed; starting the execution of the assembly code or the binary machine code in the runtime environment using the test data; and determining whether each code in the set of codes to be tested is covered according to the indication from the runtime environment.

This invention discloses a collaborative obfuscation system and method based on heterogeneous execution, relating to the field of code protection, and representing a hardware-software collaborative code protection scheme. By constructing a covert execution environment on a solid-state drive (SSD), its internal structure, communication protocols, and firmware are analyzed and functionally extended, and a dedicated instruction space is partitioned. Simultaneously, based on the LLVM compiler framework, three collaborative obfuscation algorithms—control flow flattening, spoofed control flow, and data encryption—are researched and implemented to generate obfuscated binary code and extract key elements. Furthermore, communication facilities between the host and the SSD are established, a stable interaction process is designed, and collaborative obfuscation and anti-debugging functions are implemented. This invention effectively improves the code's resistance to static analysis and dynamic debugging, offering significant advantages over classical methods and providing a more effective solution for code protection.

The application relates to the field of computer technology, in particular to a fast floating-point division and square root operation method based on a Radix4 SRT algorithm, which comprises the following steps: data preprocessing is performed on operation data to obtain operation standard data, a residual error saved in a CSA form is obtained according to an operation number of the operation standard data, an iteration part of a mantissa is obtained, a partial sum is matched with a preset QDS lookup table to obtain quotient bits / root bits, expressed in a redundant numeral base, the quotient bits / root bits expressed in the redundant numeral base are converted into a standard binary complement form quotient / root according to a fast conversion algorithm; auxiliary bits are generated according to the partial sum of the mantissa and carry information to obtain r / s bits; and finally, a division / square root result is obtained according to the r / s bits and a rounding mode. The application adopts a common lookup table mode, reduces the area requirement of different lookup tables for division and square root, can significantly save hardware resources, and can quickly judge zero remainder and negative remainder conditions in advance through a sign bit detection technology.

A method for transmitting a first number to a recipient computing machine in a distributed computing environment is proposed, which comprises: obtaining a second number corresponding to the first number, wherein the first number belongs to a first range of numbers, and the second number belongs to a second range of numbers; determining an encoding of the second number according to a binary format for encoding floating-point numbers, wherein a binary code representing a number encoded according to the format comprises a sign binary field carrying at most one sign bits encoding a sign of the number, an exponent binary field carrying one or more exponent bits encoding an exponent of a power of 2, and a fraction binary field carrying one or more significant decimal digits and transmitting, to the recipient computing machine, data representing the first number, wherein the data carries an encoding of the second number according to the format with no exponent field corresponding to the encoded second number.

This application provides an analysis method and system for obfuscated PASS based on LLVM, relating to the field of software protection technology. The method includes: extracting the target function from the obfuscated binary program, locating the position of the encrypted string within the target function, and determining the decryption logic based on the position of the encrypted string; searching for the target expression in the target function, identifying the expression logic through pattern matching, and determining the string encryption algorithm parameters based on the decryption logic and the expression logic; constructing a control flow graph based on the expression logic, identifying the control variables in the control flow graph, and generating a state transition diagram of the control variables based on the assignment sequence of the control variables; identifying the identifiers of useless basic blocks in the target function based on the state transition diagram, and determining the obfuscation implementation logic of the obfuscated binary program based on the string encryption algorithm parameters and the identifiers of the useless basic blocks. The technical solution provided by this application can achieve reverse derivation of the obfuscation implementation logic.

A method, an apparatus, and a non-transitory computer-readable storage medium for video decoding and encoding are provided. In one method for video decoding, a binary arithmetic decoder may obtain a multiple hypothesis probability of a binary symbol of a given context model of the binary arithmetic decoder according to an adaptive weight, the multiple hypothesis probability indicating a probability that the binary symbol is equal to a binary value, the binary symbol being from a plurality of binary symbols associated with the context model. Furthermore, the decoder may decode the binary symbol according to the multiple hypothesis probability.

According to various embodiments, a method for monitoring a data flow in several executed application programs is described, wherein at least some of the application programs of the several application programs are programmed in different programming languages, comprising: Transforming the program code of each of the multiple application programs into code of a predefined binary instruction format, Inserting a data flow monitoring code into the code of the specified binary instruction format in each transformed application program to generate multiple extended transformed application programs in the code of the specified binary instruction format, and executing the multiple extended transformed application programs and thereby monitoring the data flow in the multiple extended transformed application programs using the data flow monitoring code inserted in each case.