14 results about "Channel-stopper" patented technology

To provide a semiconductor device with improved HBT withstand capability. [Solution] The semiconductor device comprises a silicon carbide substrate, a field oxide film, an insulating film, and a wiring layer. The silicon carbide substrate has a first main surface and a second main surface which is the opposite surface of the first main surface. In a plan view, the second main surface has a cell region and an outer peripheral region located between the cell region and the outer peripheral edge of the second main surface. Within the silicon carbide substrate, the silicon carbide substrate has a termination structure and a channel stopper formed on the second main surface located in the outer peripheral region. In a plan view, the channel stopper is located outside the termination structure. The conductivity type of the silicon carbide substrate and the conductivity type of the channel stopper is a first conductivity type. The termination structure has a second conductivity type opposite to the first conductivity type. The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the termination structure in a plan view and at least partially overlaps the channel stopper in a plan view.

A semiconductor device, including: a semiconductor substrate having an active region and a termination region; a first semiconductor region provided in the semiconductor substrate; a second semiconductor region provided in the active region, between a front surface of the semiconductor substrate and the first semiconductor region; a vertical device structure provided in the active region; an insulating layer that covers the front surface of the semiconductor substrate in the termination region; a voltage withstanding structure provided in the termination region to surround the active region, and including a third semiconductor region; a channel stopper electrode provided on the insulating layer, closer to the semiconductor substrate than is the voltage withstanding structure; and a fourth semiconductor region provided between the front surface of the semiconductor substrate and the first semiconductor region, apart from the third semiconductor region and the contact hole on two sides of the fourth semiconductor region.

A semiconductor device (100) comprises a silicon carbide substrate (10), a field oxide film (20), an insulating film (50), and a wiring layer (60). The silicon carbide substrate comprises a first main surface (10a) and a second main surface (10b), which is opposite the first main surface. The second main surface comprises a cell region (10ba) and an outer peripheral region (10bb) located, in plan view, between the cell region and an outer peripheral edge of the second main surface. The silicon carbide substrate includes a termination structure (18) and a channel stopper (19) formed in the second main surface located in the outer peripheral region. The channel stopper is located outside the termination structure in plan view.One conductivity type of the silicon carbide substrate and one conductivity type of the channel stopper each constitute a first conductivity type. The termination structure exhibits a second conductivity type opposite to the first. The field oxide film is formed on the second main surface located in the outer peripheral region such that it overlaps the termination structure in plan view and at least partially overlaps the channel stopper in plan view.

To improve the degree of freedom in controlling the depletion layer. [Solution] The semiconductor device comprises a channel stopper region of a first conductivity type formed on the surface of the drift layer in the termination region, a first termination trench formed in the drift layer in the termination region, a plurality of termination electrodes provided within the first termination trench surrounded by a first termination insulating film, and a channel stopper electrode provided on the upper surface of the drift layer in an electrically connected state to the channel stopper region and the termination electrodes, wherein the plurality of termination electrodes include a first termination electrode and a second termination electrode.

To provide a semiconductor device and a method for manufacturing a semiconductor device that can improve yield. [Solution] Insulating layers 12 and 13 are provided on the front surface of the semiconductor substrate 11 in the edge termination region 2. Insulating layer 12 is provided inside the scribe region 3 remaining on the outer circumference of the semiconductor substrate 11 and covers the withstand voltage structure 30 and the channel stopper region 33. Insulating layer 13 is provided in the scribe region 3. The thickness t2 of insulating layer 13 is thinner than the thickness t1 of insulating layer 12. The scribe region 3 is the remainder of the scribe line of the semiconductor wafer. Because the insulating layers 12 and 13 reduce the stress on the front surface side of the semiconductor wafer, the magnitude of the stress imbalance between the front and back surfaces of the semiconductor wafer after the formation of the surface electrode 54 can be reduced compared to the case where an insulating layer of a constant thickness is provided on the front surface of the semiconductor substrate 11 in the edge termination region 2, and the amount of warping of the semiconductor wafer is reduced.

The invention discloses a charge-coupled device with a multi-well structure and a preparation method of the charge-coupled device. The epitaxial layer is arranged on the substrate; the composite well region is arranged on the epitaxial layer and comprises a first well, a second well and a third well, and the first well and the third well form a saddle point in the center of a pixel, so that well doping below a CCD pixel unit needs to be weaker than that on the two sides, a weak doping channel of the composite well region is formed, and the composite well region is used for a charge-coupled device to discharge excess charges; the CCD charge channel is arranged on the composite well region; the channel resistors are arranged on the composite well region, located on the two sides of the CCD charge channel and used for achieving isolation of the CCD charge channel between different unit columns of the charge-coupled device; the dielectric layer is arranged on the upper surfaces of the CCD charge channel and the channel resistor; and the polysilicon gate is arranged on the upper surface of the dielectric layer and is used as a functional electrode of the charge-coupled device. Therefore, the CCD device has the capability of discharging excess charges.

To provide an inexpensive semiconductor device with improved moisture resistance. [Solution] The front surface of the semiconductor substrate 40 has an outer peripheral step 25 on the channel stopper region 32 at the outer periphery of the semiconductor substrate 40, where the fourth surface 40d, which includes the scribe region 3 at the outer periphery of the semiconductor substrate 40, is recessed from the fourth surface 40d toward the chip center. The insulating layer 33 is provided with a constant thickness over the entire surface of the front surface of the semiconductor substrate 40 in the edge termination region 2. The surface protective film 34 covers the outer peripheral step 25 of the front surface of the semiconductor substrate 40 via the insulating layer 33. The upper surface of the surface protective film 34 has a fifth upper surface 34e that slopes more gently and has a smaller inclination angle than the outer peripheral step 25 on the portion of the outer peripheral step 25 of the front surface of the semiconductor substrate 40. The surface protective film 34 terminates toward the chip center toward the edge of the semiconductor substrate 40, exposing the scribe region 3, and has a tapered outer end surface 34f on the fourth surface 40d of the front surface of the semiconductor substrate 40.

A semiconductor apparatus includes: a semiconductor substrate; a diffusion layer; a first depletion prevention region; a channel stopper electrode, a monitor electrode and an insulating film. The inner edge portion of the monitor electrode is positioned between the diffusion layer and the first depletion prevention region. A distance between the outer edge portion of the channel stopper electrode and the inner edge portion of the monitor electrode is a first distance. A distance between the diffusion layer and the first depletion prevention region is a second distance. The first and second distances are set so that a discharge voltage between the channel stopper electrode and the monitor electrode becomes greater than an avalanche breakdown voltage at a PN junction portion of the diffusion layer and the semiconductor substrate.

The present invention improves the degree of freedom of control of a depletion layer. The semiconductor device includes: a first conductivity-type channel cutoff region formed on a surface layer of a terminal region of a drift layer; a first terminal trench formed at the terminal region of the drift layer; a plurality of terminal electrodes provided within the first terminal trench in a state of being surrounded by a first terminal insulating film; and a channel cutoff electrode provided on the drift layer in a state of being electrically connected to the channel cutoff region and the terminal electrodes, the plurality of terminal electrodes including a first terminal electrode and a second terminal electrode.

A semiconductor device of the present application includes a silicon carbide substrate, a field oxide film, an insulating film, and a wiring layer. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The second main surface has a cell region and a peripheral region between the cell region and a peripheral edge of the second main surface when viewed in plan. The silicon carbide substrate has a termination structure and a channel stopper ring formed in the second main surface in the peripheral region. The channel stopper ring is located outward of the termination structure when viewed in plan. The silicon carbide substrate and the channel stopper ring have a first conductivity type. The termination structure has a second conductivity type opposite to the first conductivity type. The field oxide film is formed on the second main surface in the peripheral region so as to overlap the termination structure when viewed in plan and at least partially overlap the channel stopper ring when viewed in plan.

Method for manufacturing a semiconductor device, comprising: Forming a channel stopper area (191) extending from a planar, horizontal first main surface (701) into a component layer (710) of a first conductivity type in an edge termination area (690) adjoining a saw track area (800) of a component area (600), wherein the formation of the channel stopper area (191) comprises forming a first dopant mask (410) on the first main surface (701) and introducing a first dopant (195) through a mask opening (415) of the first dopant mask (410), wherein the first dopant (195) is introduced through sections of the first main surface (701) exposed through the mask opening (415) of the first dopant mask (410); and Forming a doped area (120) extending from the first main surface (701) into the component layer (710) in the component area (600), wherein the channel stopper area (191) is formed by means of a photolithographic process which is carried out prior to a first photolithographic process for introducing dopants into a section of the component area (600) outside the channel stopper area (191), and where in the component area (600) a maximum vertical extent (v1) of the channel stopper area (191) perpendicular to the first main surface (701) is greater than a maximum lateral extent (w1) of the channel stopper area (191) in the component area (600) parallel to the first main surface (701).

A semiconductor device includes: a channel stopper region of a first conductivity type formed on a surface layer of a drift layer in a termination region; a first termination trench formed in the drift layer in the termination region; a plurality of termination electrodes provided in the first termination trench while being surrounded by a first termination insulating film; and a channel stopper electrode provided on an upper surface of the drift layer while being electrically connected to the channel stopper region and the termination electrodes, wherein the plurality of termination electrodes include a first termination electrode and a second termination electrode.

A semiconductor device includes a silicon carbide substrate, a field oxide film, an insulation film, and a wiring layer. The silicon carbide substrate includes a first main surface, and a second main surface being an opposite surface of the first main surface. The second main surface includes a cell region, and an outer peripheral region located between the cell region and an outer peripheral edge of the second main surface in plan view. The silicon carbide substrate includes a termination structure and a channel stopper that are formed in the second main surface located in the outer peripheral region in the silicon carbide substrate. The channel stopper is located outside the termination structure in plan view. A conductivity type of the silicon carbide substrate and a conductivity type of the channel stopper are each a first conductivity type.

The present invention relates to a high-voltage terminal structure for a power semiconductor device and a manufacturing method thereof. This high-voltage terminal structure includes a semiconductor body having a first conductivity type, a junction terminal extension region having a second conductivity type, a heavily doped channel stopper region having a first conductivity type, and a plurality of field plates. The junction terminal extension region is formed in the semiconductor body, wherein the junction terminal extension region is adjacent to an active region of the power semiconductor device. The heavily doped channel stopper region is formed in the semiconductor body, wherein the heavily doped channel stopper region is separated from the junction terminal extension region. The plurality of field plates are formed on the junction terminal extension region. The present invention also provides a method for manufacturing a high-voltage terminal structure for a power semiconductor device.