62 results about "Channel-stopper" patented technology

In bottom-gate-type thin film transistors used in a liquid crystal display device, a channel stopper layer is formed on a poly-Si layer thus stabilizing a characteristic of the thin film transistor. The channel stopper layer is formed into a desired shape by wet etching, and the poly-Si layer is formed into a desired shape by dry etching. By applying side etching to the channel stopper layer, a peripheral portion of the poly-Si layer is exposed from the channel stopper layer, and this region is brought into contact with an n+Si layer. Due to such constitution, ON resistance of the thin film transistor can be decreased thus increasing an ON current which flows in the thin film transistor.

In a photoelectric conversion device with a photoelectric conversion region for accumulating electric charges that correspond to incident light and an amplifying filed effect transistor into which a signal charge from the photoelectric conversion region is inputted, the photoelectric conversion region is surrounded by a potential barrier region (a selectively oxidized film and a channel stopper), a nick region (overflow channel) is formed in a part of the potential barrier region, and a drain region of the field effect transistor that has the same conductivity type as the photoelectric conversion region is placed next to the nick region. Thus excess carriers are prevented from flowing into adjacent pixels or other floating regions.

A semiconductor device includes: a semiconductor substrate having a main surface having an element formation region, a guard ring, a guard ring electrode, a channel stopper region, a channel stopper electrode, and a field plate disposed over and insulated from the semiconductor substrate. The field plate includes a first portion located between the main surface of the semiconductor substrate and the guard ring electrode, and a second portion located between the main surface of the semiconductor substrate and the channel stopper electrode. The first portion has a portion overlapping with the guard ring electrode when viewed in a plan view. The second portion has a portion overlapping with the channel stopper electrode when viewed in the plan view. In this way, a semiconductor device allowing for stabilized breakdown voltage can be obtained.

In one surface of a semiconductor substrate, an n⁻ layer, a p base layer, a p well layer, another p well layer, a channel stopper layer, an emitter electrode, a guard ring electrode, and a channel stopper electrode for example are formed. In the other surface of the semiconductor substrate, an n⁺ buffer layer, a p⁺ collector layer, and a collector electrode are formed. In a curved corner of the p well layer, a p low-concentration layer having a lower impurity concentration than the impurity concentration of the p well layer is formed from the surface to a predetermined depth.

The invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type; a third semiconductor layer of a second conductivity type; a fourth semiconductor layer of the first conductivity type; first trenches which penetrate the fourth semiconductor layer and the third semiconductor layer to reach the second semiconductor layer; a second trench which penetrates the fourth semiconductor layer and the third semiconductor layer, on a side closer to a termination than the first trenches, to reach the second semiconductor layer, the second trench dividing the fourth semiconductor layer and the third semiconductor layer into a element part including a region wherein the first trenches are formed and a termination part; an insulating film; a gate electrode; a first main electrode; a second main electrode; a channel stopper layer provided in the second trench via the insulating film; and a channel stopper electrode provided on the termination part of the third semiconductor layer and the termination part of the fourth semiconductor layer and connecting the channel stopper layer and the termination part.

A stopper structure includes a wall defining an opening. A rotary electronic component has a rotational shaft extending through the opening. A channel stopper has a tubular body and an engagement projection. The tubular body is detachably mounted on the rotational shaft and is inhibited from rotating relative thereto. The engagement projection extends from an end of the tubular body in an axial direction and a radial direction with respect to the rotational shaft. A rotary operation member is detachably mounted on the rotational shaft and the tubular body and is inhibited from rotating relative thereto. The rotary operation member has an axial hole in which at least portions of the rotational shaft and the tubular body fit. A limiting portion provided on the wall is engageable with the engagement projection for liming a range of rotation of the rotational shaft.

A semiconductor device according to the present invention includes a p-type semiconductor substrate, a first n-type collector diffusion layer formed in the p-type semiconductor substrate, a deep trench formed in the p-type semiconductor substrate so as to surround the first n-type collector diffusion layer, a p-type channel stopper layer formed beneath the deep trench, and an n-type diffusion layer formed between a sidewall of the deep trench and the first n-type collector diffusion layer.

A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. In a fifth aspect, the capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. In sixth and seventh aspects, wiring is provided. In the sixth aspect, an aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; in the seventh aspect, a refractory metal, or a refractory metal suicide QSi.sub.x, where Q is a refractory metal and 0<x<2, is used as a protective layer, for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.

A transfer gate is formed such that both end portions thereof in a second direction, which crosses a first direction in which a photodiode and a floating diffusion layer that is formed with a distance from the photodiode are arranged, are located inside boundaries with element isolation regions. Channel stopper layers are formed on surface portions of a device region in the vicinity of lower parts of both end portions of the transfer gate in the second direction in such a manner to extend to the boundaries with the element isolation regions.

An embodiment of array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type and housing an anode region, of a second conductivity type, facing a top surface of the body, a cathode-contact region, having the first conductivity type and a higher doping level than the body, facing a bottom surface of the body, an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the anode region and the cathode-contact region. The insulation region is formed by a first mirror region of polycrystalline silicon, a second mirror region of metal material, and a channel-stopper region of dielectric material, surrounding the first and second mirror regions.

A method of producing a semiconductor device includes the steps of forming a trench in a semiconductor substrate of a first conductive type so that an active region having a first portion and a second region is formed; implanting a first impurity of the first conductive type at an implantation angle between 30 degrees and 45 degrees relative to a normal line in an implantation direction rotating relative to the normal line so that a first channel diffusion region and a channel stopper region of the first conductive type are formed; filling the trench with an insulation layer; implanting a second impurity of a second conductive type so that a second channel diffusion region of the second conductive type is formed; forming a gate insulation film on the first portion and the second portion; and forming a gate electrode on the gate insulation film.

On the principal surface of a silicon substrate, a side spacer made of silicon nitride is formed on the side wall of a lamination including a silicon oxide film, a silicon nitride film and a silicon oxide film. Thereafter, a channel stopper ion doped region is formed by implanting impurity ions by using as a mask the lamination, side spacer and resist layer. After the resist layer and side spacer are removed, a field oxide film is formed through selective oxidation using the lamination as a mask, and a channel stopper region corresponding to the ion doped region is formed. After the lamination is removed, a circuit device such as a MOS type transistor is formed in each device opening of the field oxide film.

A semiconductor device of an embodiment includes a p⁺-type region selectively disposed in a surface of an n-type silicon carbide epitaxial layer disposed on an n⁺-type silicon carbide substrate, an element structure that includes a source electrode and a p⁺-type region that form a metal-semiconductor junction on the n-type silicon carbide epitaxial layer, a p⁻-type region and another p⁻-type region that surround the periphery of the element structure, and an n⁺-type channel stopper region that surrounds the periphery of the p⁻-type regions so that the n-type silicon carbide epitaxial layer is therebetween. The n⁺-type channel stopper region has a second n⁺-type channel stopper region whose impurity concentration is high, and a first n⁺-type channel stopper region that encompasses the second n⁺-type channel stopper region and whose impurity concentration is lower than that of the second n⁺-type channel stopper region.

In one surface of a semiconductor substrate, an active region in which main current flows and an IGBT is disposed is formed. A termination structure portion serving as an electric-field reduction region is formed laterally with respect to the active region. In the termination structure portion, a porous-oxide-film region, a p-type guard ring region, and an n+-type channel stopper region are formed. A plurality of floating electrodes are formed to contact the surface of the porous-oxide-film region. Another plurality of floating electrodes are formed to contact a first insulating film.

A semiconductor device in which a desired device is formed, comprising a semiconductor substrate having a first impurity region of a first conductivity type provided around an edge of a region in which the desired device is formed, and a second impurity region of the first conductivity type provided in a scribe region of the semiconductor substrate; wherein a channel stopper is formed between the first impurity region and the second impurity region.

To provide a method of forming a field oxide film capable of simply and accurately forming a channel stopper region separately from an element hole immediately under the field oxide film. On the principal surface of a silicon substrate, a side spacer made of silicon nitride is formed on the side wall of a lamination including a silicon oxide film, a silicon nitride film and a silicon oxide film. Thereafter, a channel stopper ion doped region is formed by implanting impurity ions by using as a mask the lamination, side spacer and resist layer. After the resist layer and side spacer are removed, a field oxide film is formed through selective oxidation using the lamination as a mask, and a channel stopper region corresponding to the ion doped region is formed. After the lamination is removed, a circuit device such as a MOS type transistor is formed in each device opening of the field oxide film.