7 results about "Frame synchronization (video)" patented technology

The application discloses an ultra-high-definition video decoding and distribution system supporting AVS3 and double VIVID, and particularly relates to the technical field of digital video processing, and comprises a code stream receiving and analyzing module, a double VIVID metadata tightly coupled processing module, a metadata synchronous extraction module and an intelligent distribution interface module. The coding standard of a heterogeneous input code stream is automatically identified through a feature fingerprint database, and the TLV format and a differentiated embedding strategy are used to realize the tight coupling and synchronization of HDR Vivid and Audio Vivid metadata and video frames. In combination with a priority buffer queue and a PTS matching technology, the metadata is accurately extracted at a decoding end, and finally adaptive tone mapping and protocol conversion distribution are executed according to terminal EDID feedback. The application solves the problems of difficult multi-source heterogeneous stream identification, low double VIVID metadata and video frame synchronization accuracy and poor terminal adaptation, and ensures the consistency of the immersive experience of ultra-high-definition audio and video under different distribution links.

The present disclosure provides a touch and display driver integrated (TDDI) frame synchronization updating method, device and equipment. The method comprises: determining an input frame synchronization signal Vsync_in; generating a system frame synchronization signal Vsync_sys according to the input frame synchronization signal Vsync_in; and applying the system frame synchronization signal Vsync_sys to each functional module of the TDDI to perform frame synchronization. Thus, the Vsync_in is delayed to generate the Vsync_sys, and then the system frame synchronization signal Vsync_sys is applied to each functional module of the TDDI chip, so that the command use error caused by using the video attribute setting instruction at the start of the Vsync_in signal of the current frame video while the DE_out signal of the previous frame video is not transmitted completely can be avoided, so that the accurate use of the command in the same frame video is ensured, and then the normal display of the video is ensured.

Embodiments of the present application disclose a multi-camera frame synchronization method and device and a storage medium, and are applied to the technical field of images. A slave camera in a multi-camera system acquires first timestamp information of each frame in a master video frame sequence and second timestamp information of each frame in a slave video frame sequence, and calculates a first time interval of adjacent frames in the master video frame sequence and a second time interval of adjacent frames in the slave video frame sequence based on the information, so that the frame rate of the slave camera is set to be the same as that of the master camera. On this basis, the frame rate of the slave camera is adjusted in combination with a timestamp difference between the second timestamp information of a specific frame in the slave video frame sequence and the first timestamp information of a first reference frame in the master video frame sequence and the frame interval of adjacent frames, so as to gradually realize frame synchronization of the master and slave cameras, so that each slave camera and the master camera can simultaneously capture a target scene at the same time, and the phenomenon of splitting in later picture splicing is avoided.

The invention discloses an annular buffer data transmission method, chip and system in a QSPIVideo mode. A host sends a frame synchronization instruction packet to a display driving chip through a QSPI interface; after the frame synchronization instruction packet, the host sends a line synchronization instruction packet to the display driving chip through the QSPI interface; a host continuously writes continuous data blocks comprising multiple rows of pixel data into an annular buffer of a display driving chip through an interface in a direct memory access (DMA) mode, and the continuous data blocks do not comprise row synchronization instruction packets; the display driving chip stores the received continuous data blocks in an annular buffer, reads pixel data line by line from the annular buffer, and generates corresponding line synchronizing signals to drive the display panel to display multiple lines of pixel data; according to the method, the annular buffer is introduced and the communication protocol is optimized, so that the data transmission efficiency is greatly improved and the host load is reduced on the premise that the chip cost is not obviously increased.

The present disclosure relates to the technical field of videos, and provides a video synchronization method and apparatus, an electronic device, and a storage medium. The method comprises: measuring a reference frame synchronization signal by using a master clock, and calculating a first frequency multiple between a video clock of a video interface and the master clock on the basis of the measurement result; generating two frequency multiples closest to the first frequency multiple, and generating a first adjustment clock and a second adjustment clock of different frequencies on the basis of the two frequency multiples; generating a first target synchronization signal of the master clock and a second target synchronization signal of the video clock on the basis of the reference frame synchronization signal and a video parameter of the video interface; comparing the phase of the first target synchronization signal with the phase of the second target synchronization signal; and switching, on the basis of the comparison result, the video clock to the first adjustment clock or the second adjustment clock when a switchable moment is reached, so that a first frame synchronization signal generated on the basis of the master clock is synchronized with a second frame synchronization signal of the video clock, and the first frame synchronization signal is synchronized with the reference frame synchronization signal. The present disclosure can achieve complete synchronization between video data of a plurality of video interfaces.

This invention provides a video synchronization method, apparatus, electronic device, and storage medium, relating to the field of video technology. The method includes: measuring a reference frame synchronization signal using a master clock; calculating a first harmonic of the video clock of the video interface with respect to the master clock based on the measurement result; generating two harmonics closest to the first harmonic; and generating a first adjustment clock and a second adjustment clock of different frequencies based on these two harmonics. Based on the reference frame synchronization signal and the video parameters of the video interface, a first target synchronization signal of the master clock and a second target synchronization signal of the video clock are generated; their phases are compared; and based on the comparison result, when a switchable time is reached, the video clock is switched to either the first adjustment clock or the second adjustment clock, so that the first frame synchronization signal generated based on the master clock is synchronized with the second frame synchronization signal of the video clock, and the first frame synchronization signal is synchronized with the reference frame synchronization signal. This invention can achieve complete synchronization between video data from multiple video interfaces.

The application relates to a black field processing method and device, electronic equipment and a storage medium. The method acquires a first frame synchronization signal and a second frame synchronization signal; according to the time difference between the first frame synchronization signal and the second frame synchronization signal, the frame rate of a video picture after a current video picture output to a display screen by a control system is adjusted to a preset frame rate, so that the stability of the frame rate of the video picture output by the control system is ensured, and the stability of a first black field time between two adjacent video pictures is ensured; on this basis, the second black field time is scattered into the gray scale decoding time of a sub field. Since the second black field time is scattered into the gray scale decoding time of the sub field, the first black field time is effectively reduced, and the display effect of the display screen is improved.