A
noise attenuator
loop filter for PLL applications that allows a full on-
chip integration of the
loop filter capacitors, while ensuring a low output
clock phase noise (
jitter) is disclosed. A
voltage attenuator (A) is inserted between the
loop filter (passive or active) and the controlled oscillator. The attenuator attenuates the
noise coming from the loop filter. In case of a passive RC filter, the series
resistor noise power is attenuated by A2 times, allowing the usage of a
resistor that is A2 times larger and therefore the loop filter capacitors result A2 times smaller (easy to integrate on-
chip). The relatively low value
capacitor allows the usage of thick-
oxide accumulation-mode
MOSFET capacitors that take a reasonable low area, have a good
linearity, are isolated from the substrate by the grounded N-well, and have negligible
gate leakage current. Several embodiments of the noise attenuator are proposed for different practical applications:
clock generation for digital circuits, frequency translation, low or high supply
voltage, narrow or wide frequency range, processes with or without isolated well devices, processes with or without polysilicon resistors, and medium or high reference spurs rejection.