5 results about "Pre testing" patented technology

A testing method and system for electronic devices are provided. The testing method for electronic devices includes receiving multiple first test data for multiple first test cases and multiple second test data for multiple second test cases; generating multiple first local scores based on the multiple first test data; generating multiple second local scores based on the multiple second test data; generating a global score for a common test case of the multiple first test cases and the multiple second test cases; replacing at least some of the multiple first local scores with the global score to generate multiple first test scores; replacing at least some of the multiple second local scores with the global score to generate multiple second test scores; and performing a first mutation operation based on a first optimal test case corresponding to the highest score among the multiple first test scores to generate a first pre-test set.

This invention relates to the field of electrical safety testing technology, and discloses a comprehensive testing device and method for power supply filters. The method includes: performing closed-loop correction of the contact impedance of the test circuit before applying the test voltage; intelligently selecting parallel or sequential excitation mode to apply high voltage based on pre-test results; acquiring leakage current waveforms in real time during the test, comparing them with preset insulation failure precursor characteristics, and rapidly cutting off the high voltage within microseconds through an independent hardware channel during matching; calculating the dispersion of batch leakage current after the test and comparing it with a threshold adaptively updated based on historical data. The corresponding device includes a high-voltage matrix switch network, an adaptive tooling matrix, a safety monitoring module, and a host computer. This invention achieves reliable test connection assurance, proactive safety protection during the test process, and intelligent optimization capabilities for the test strategy.

This application discloses a method, apparatus, device, and medium for predicting the number of erase / write cycles of flash memory. The method includes: performing a limited number of cycles of room temperature and high temperature testing on selected flash memory chips to obtain pre-test characteristic parameters, and determining bad block judgment parameters based on the pre-test characteristic parameters; determining logical bad blocks on the selected flash memory chips based on the bad block judgment parameters to obtain the number of logical bad blocks with a limited number of cycles at room temperature and the number of logical bad blocks with a limited number of cycles at high temperature; performing a high temperature cycle test on the selected flash memory chips and determining physical bad blocks to obtain the number of high temperature cycle erase / write cycles; performing the same room temperature and high temperature tests on the pre-test flash memory chips to obtain the number of pre-test logical bad blocks with a limited number of cycles at room temperature and the number of pre-test logical bad blocks with a limited number of cycles at high temperature; and determining the target number of erase / write cycles for the pre-test flash memory chips based on the obtained data. This technical solution achieves accurate evaluation of the number of erase / write cycles of flash memory chips, reduces losses, and improves efficiency.

This disclosure provides a pre-testing method and system for storage devices, applicable to testing systems. After powering on the test board, the control device sets the enable pins of each storage device under test (DUT) to a pre-test level, causing multiple DUTs to enter a pre-test mode instead of the target test mode. Next, the control device performs a scan operation on the multiple DUTs, switching the scan pins corresponding to the DUTs from a first level to a second level, reading the indicator signals output by the DUTs through indicator pins, and restoring the corresponding scan pins to the first level. Finally, the control device determines the contact state between each DUT and its corresponding test socket based on the indicator signals, and determines whether to allow multiple DUTs to enter the target test mode based on the contact state. This disclosure achieves non-invasive contact detection through pin level combinations, preventing DUTs with abnormal contact from entering the target test mode, thus improving test yield and efficiency.