55 results about "Printed circuit board design" patented technology

The invention relates to a geometric optimization method for copper sheet layout, computer equipment, a storage medium and a product. The geometric optimization method is used for optimizing an acute angle structure of a copper sheet in the design and manufacturing process of a printed circuit board, and comprises the following steps: providing a polygonal copper sheet area, and obtaining vertex coordinate data of the polygon; constructing a first geometric model corresponding to the polygon according to the vertex coordinate data, and traversing vertexes of the polygon in the first geometric model; defining two adjacent vertexes of the vertexes as a preorder vertex and a postorder vertex respectively, and judging whether an included angle formed by connecting lines among the preorder vertex, the vertexes and the postorder vertex is an acute angle or not; when the included angle is an acute angle, calculating a common tangent circle corresponding to the included angle, and constructing a second geometric model corresponding to the common tangent circle; and based on the second geometric model, carrying out smoothing processing on the area with the included angle being the acute angle to obtain an optimized copper sheet layout.

The invention discloses a design method of a printed circuit board and electronic equipment. The design method comprises the following steps: acquiring initial position information and initial angle information of a target element of the printed circuit board; according to a preset objective function, gradient iteration is carried out on the initial position information and the initial angle information, fine adjustment position information and fine adjustment angle information are obtained, and the preset objective function is used for minimizing the wiring length based on the position information and the angle information; according to preset element layout constraints, the fine adjustment position information and the fine adjustment angle information, the target optimization function is solved, target position information and target angle information are obtained, and the preset element layout constraints at least comprise element spacing constraints, element non-overlapping constraints and element boundary constraints; the target optimization function is used for indicating the wiring length and the wiring reasonability of the element, and the target position information and the target angle information enable the target optimization function to obtain a minimum solution; and adjusting the target element on the printed circuit board according to the target position information and the target angle information.

The invention provides a differential pair ordered escape wiring method based on improved Monte Carlo tree search, and aims to solve the problem of path optimization of differential pair signal wiring in the design of a high-density printed circuit board. According to the method, MCTS and Q-learning reinforcement learning technologies are combined, a wiring intermediate point does not need to be preset, and a wiring path can be dynamically generated under a grid pin array and a staggered pin array. Through multiple times of simulation and backtracking, the method can effectively process complex pin arrangement and blocking areas, ensures wiring length matching and reduces electromagnetic interference. Meanwhile, according to the method, a Q table obtained through one-time Q learning can serve as the basis for simulation of all the nodes of the Monte Carlo tree, all the expansion nodes are simulated in the simulation stage, and the defect that the time of the MCTS simulation part is long is overcome. According to the method, the MCTS search capability and the convergence speed are improved by adopting a gradual widening strategy. The method is suitable for PCB design of high-performance electronic equipment, such as the fields of communication, computers and avionics.

A power tool with a combined printed circuit board (PCB) that reduces internal wiring of the power tool and provides a large amount of air flow to internal components. In some instances, the combined PCB has a surfboard shape and includes a motor control unit and power switching elements (Field Effect Transistors or FETs). The combined surfboard PCB is located above the trigger, but below the motor and drive mechanism. In other instances, the combined PCB has a doughnut shape and is located coaxially with a motor shaft. The combined PCB may be positioned between a doughnut-shaped control PCB and the motor.

The invention discloses a Cadence Skill-based automatic creation method and system for a depth-controlled milling groove distribution forbidding area of a PCB connector, and a medium, and belongs to the technical field of electronic printed circuit board design, and the method comprises the steps: generating the lamination number and depth of the milling distribution forbidding area corresponding to a hollow area according to the creation data, processing parameters, geometric shape and installation hierarchy of a target PCB connector; carrying out groove milling processing on the target PCB connector according to the lamination number and depth of the milling distribution forbidding area, and simultaneously carrying out error reporting prompt on wiring, via holes and copper sheets in the hollowed area; the overhanging amount of the pins of the processed target PCB connector is greater than or equal to a preset welding pin safety distance, and the residual board thickness of the non-milling area is smaller than the effective embedding length of the pins. According to the invention, the problems of low efficiency, high miscalculation risk, poor groove milling consistency and signal failure caused by the fact that the establishment of the existing PCB connector pin distribution forbidding area depends on manual operation are solved.

The disclosed computer-implemented method for automatically generating a printed circuit board design includes executing, by at least one processor based on input parameters, a grouping operation that identifies network shapes defining regions occupied by corresponding networks for one or more layers of an integrated circuit package. The method additionally includes identifying, by the at least one processor based on the identified network shapes, connections of the integrated circuit package. The method also includes automatically generating, by the at least one processor and based on the identified connections, a printed circuit board design. Various other methods, systems, and computer-readable media are also disclosed.

The present application relates to the technical field of printed circuit board design, and discloses a via arrangement method, device, equipment and storage medium for a printed circuit board, including: for two signal vias corresponding to a group of high-speed differential signals, a ground network return via is arranged at the middle position between the two signal vias; the two signal vias share one ground network return via; for four signal vias corresponding to two groups of high-speed differential signals, a ground network return via is arranged at the middle position among the four signal vias; wherein, the four signal vias share one ground network return via. In the design of the via arrangement structure for high-speed differential signals to change layers, the present application only arranges one corresponding ground network return via for one or two groups of high-speed differential signals, that is, enables two or four signal vias to share one ground network return via, thereby simplifying the single-board design to improve the space utilization rate of the single board, and reducing the space occupied by high-speed differential signals while meeting the electrical performance requirements.

The utility model provides an intelligent closestool and a miniature capacitance type foot kicking induction device thereof, and relates to the technical field of capacitance type induction, the device adopts a double-layer printed circuit board design, the superposed connection is realized through a half-hole process, the module volume is effectively reduced, and the induction capability and the electromagnetic compatibility are enhanced at the same time. A power management unit and a control unit of the device are integrated on one PCB, and a copper foil layer is arranged on the other PCB and is responsible for sensing a human body approaching signal; according to the structural design, the device can maintain stable detection capability within a preset sensing distance, and can maintain high performance even in a severe environment. Simply speaking, due to the self-adaptive capability of the device, the functions of automatic cover turning, automatic flushing, noctilucent lighting and the like can be more reliably realized in the intelligent closestool, and the problems of large size, short sensing distance, poor electromagnetic compatibility and tedious manufacturing process of a capacitive sensing module in the prior art are effectively solved.

The invention discloses a broadband high-gain flatness near-field tangential electric field probe integrated with a balance transition structure, and relates to the field of electromagnetic compatibility and electromagnetic field near-field testing. The probe is designed based on four layers of printed circuit boards, and at least comprises a coupling tip, a balance transition structure, a ferry edge structure, a signal via hole and a side plug-in connector. The hook type metal patch is connected to the twisted crossed dipole through the via hole array to form a capacitive loading effect, so that the sensitivity of the probe is improved; a balanced transition structure based on microstrip-slot transition converts differential mode current generated by the twisted and crossed dipoles into single-ended common mode output current, and the test is simplified; the edge transition structure based on Chebyshev gradual transition design reduces impedance mismatch between the balance transition structure and the side plug-in connector, and inhibits ringing ripples in probe frequency response. The tangential electric field probe disclosed by the invention has the advantages of wide frequency band, high gain flatness, low cost and the like, and is convenient for engineering popularization.

The utility model discloses a three-phase bridge type charging module printed circuit board, and belongs to the field of circuit board design. Through the optimized three-phase bridge type charging module printed circuit board design, the overall performance of the charging module is improved. According to the design, the printed circuit board is divided into three areas which respectively undertake input, power conversion and output functions, so that the current stability and efficient energy conversion are ensured. A silicon carbide MOS tube and an LLC capacitor are reasonably configured in the first printing area, so that the current processing capacity of the input end is improved. And the second printing area realizes efficient power supply conversion through the layout of an LLC resonant inductor, a capacitor and a transformer, and is matched with the DSP control module to ensure accurate regulation and control of the power supply. And the third printing area focuses on current rectification, filtering and output, and the heat dissipation capability and the electrical stability of the module are enhanced through optimal configuration of capacitors, cooling fins and inductors. In addition, the six silicon carbide MOS tubes are adopted, so that the switching loss is reduced, the overall efficiency of the module is further improved, and energy waste is reduced. According to the structural design, the working efficiency, the heat dissipation performance and the stability of the charging module are effectively improved, and long-time efficient and stable operation of the charging module is ensured.

The present disclosure relates to an AI-enabled Cadence SKILL automation development method and system. The method comprises: in response to a code development request input by a user through a command line interface, generating a first code script file including a first target code based on a code generator; generating a start script file based on the first code script file; closing all currently running printed circuit board design software processes, calling the printed circuit board design software, and controlling the printed circuit board design software to load and run the first target code based on the start script file; obtaining a log file generated by the printed circuit board design software and loading and running result information of the first target code; determining a first identification result of whether the first target code has an error according to the log file and the loading and running result information of the first target code; and in the case that the first identification result is that there is an error, repairing the first target code based on the code generator and generating a second code script file including a second target code.

The invention discloses a wireless motion control robot printed board system and method, and belongs to the technical field of robot control circuit and printed circuit board design. A single power supply input is combined with a cascade step-down circuit to provide required voltages for different modules respectively; a motor power supply is arranged on the top layer of a PCB in a wiring mode, PWM control signals are arranged on the bottom layer in a wiring mode, and physical isolation of power and signals is achieved. A switchable wireless communication module is integrated, and physical switching is carried out between a wireless control channel and a firmware downloading channel through a mode selection switch. The problems that in the prior art, a single power supply cannot stably supply power to a multi-voltage module, power and signals are arranged on the same layer, and consequently control signals are interfered are solved, stable power supply of the single power supply to the whole system is achieved, and the equipment size and wiring complexity are reduced; power supply ripples and signal interference are remarkably reduced, and the control precision is improved; wireless remote control and disassembly-free program updating are supported, and the deployment flexibility of the robot in a complex scene is enhanced.

The application proposes a differential pair ordered escape routing method based on improved Monte Carlo tree search, aiming at solving the path optimization problem of differential pair signal routing in high-density printed circuit board design. The method combines MCTS and Q-learning reinforcement learning technology, does not need to set the intermediate point of routing in advance, and can dynamically generate routing path under grid pin array and staggered pin array. Through multiple simulation and backtracking, the method can effectively handle complex pin arrangement and blocked area, ensure the matching of routing length and reduce electromagnetic interference. At the same time, the method only needs the Q table obtained by Q learning once, which can be used as the basis for simulation of all nodes of Monte Carlo tree, and all expanded nodes are simulated in the simulation stage, overcoming the long simulation time of MCTS. The step-by-step widening strategy adopted by the application accelerates the search ability and convergence speed of MCTS. The application is suitable for PCB design of high-performance electronic equipment, such as communication, computer and avionics field.

To hold a degree of freedom of design of a printed wiring board at a high level.SOLUTION: A method for manufacturing a printed wiring board includes: preparing a copper-clad laminate; dividing a high density area into a first area and a second area other than the first area; forming a first through hole in a first area of a low density area and the high density area of the copper-clad laminate; forming a first through hole conductor on the inner wall of the first through hole and a copper foil; filling the first through hole with a first resin; polishing the first through hole conductor on the first resin and the copper foil, and forming a first intermediate body; forming a second through hole in a second area of a high density area of the first intermediate body; forming a second through hole conductor on the inner wall of the second through hole and the surface of the first intermediate body; filling the second through hole with a second resin; and polishing the second through hole conductor on the second resin and the first intermediate body, and forming a second intermediate body.SELECTED DRAWING: Figure 1

The invention relates to the technical field of printed circuit board design. In particular to a PCB redundant loop automatic detection and repair method, device, equipment and medium, and the method comprises the steps: extracting corresponding signal characteristic parameters from design file information based on loop structures, calculating the signal integrity influence value of each loop structure according to the signal characteristic parameters, and calculating the signal integrity influence value of each loop structure according to the signal integrity influence value. When the signal integrity influence value is lower than the signal integrity threshold value, determining that a corresponding loop structure is a redundant loop, generating repair suggestion information according to a line connection relation of the redundant loop, correcting the line connection relation in the design file information based on the repair suggestion information, forming corrected design file information, and outputting the corrected design file information. And according to the corrected design file information, obtaining a signal integrity verification result, and when the signal integrity verification result meets preset signal integrity and time sequence requirements, outputting repair completion information. The method has the effect of improving the signal integrity of the PCB.

The application discloses a board card design method and electronic equipment, and relates to the field of printed circuit board design. The method comprises the following steps: obtaining a design file of a board card, wherein the design file comprises first electrical parameters and first structural parameters of a first component on the board card; processing the first electrical parameters and the first structural parameters to obtain a first identifier corresponding to the first component; obtaining current second electrical parameters, second structural parameters and a second identifier of the first component in a feature library; determining that the first component in the design file has been updated in the feature library when the first identifier is different from the second identifier; determining first difference information between the first electrical parameters and the second electrical parameters, and second difference information between the first structural parameters and the second structural parameters; and determining risk information of the first component that is not updated in the design file based on the first difference information and the second difference information. The method can solve the problem that the packaging update cannot be identified in time in the related art.

The invention discloses a three-electrode eye physiological electricity detection circuit and system. The circuit comprises a first test electrode, a second test electrode, a reference electrode, an acquisition circuit, a signal processing unit and a battery. The first test electrode and the second test electrode are used for reading and transmitting eye physiological electric signals, and the reference electrode is used for denoising the signals; an integrated flexible printed circuit board design is adopted, a differential amplifier, a subtracter, a precise rectifying circuit, an alternating current coupling circuit, a first-order RC low-pass filter and an adjustable resistance amplifier are integrated, and the equipment size is remarkably reduced. According to the invention, a light-weight and high-precision solution is provided for eye physiological electrical detection, the technical blank of home health monitoring is filled, and a new application scene is developed for the man-machine interaction field. The design concept can be further popularized to other physiological electric signal detection systems, and fusion development of medical electronics and intelligent hardware is promoted.

The invention discloses a design method, a design device, electronic equipment and a computer program product, and is applied to the technical field of circuit design, and the method comprises the steps: building a transmission line link channel according to a transmission line model meeting the initial board layout requirements of a printed circuit board, and obtaining a transmission line link model; optimizing the transmission line link model by taking the signal integrity as an optimization target to obtain an optimized transmission line link model; respectively building via hole models of different via hole designs to the optimized transmission line link model to obtain a plurality of printed circuit board target design models representing different designs; and determining an optimal printed circuit board design based on the signal integrity simulation result of each printed circuit board target design model. According to the method and the device, a model building link in a PCB design process is simplified, and feasibility verification of key parts in the PCB design is reserved at the same time. And while the design period is shortened, the reliability of the PCB design in the aspect of signal integrity can be ensured as much as possible.

Optoelectronic device (500) with a printed circuit board (600) designed as a DCB (direct copper bonding) printed circuit board with a layered composite of copper, an insulator and another layer of copper or as a metal core board, and with a plurality of optoelectronic components (100), wherein the optoelectronic components (100) each have a housing (110) comprising a base (200) with a top (201) and a bottom (202) and a cap (300), wherein the optoelectronic components (100) each have a laser chip (400) which is arranged between the top (201) of the socket (200) and the cap (300), wherein a first solder contact surface (210) and a second solder contact surface (220) are formed on the underside (202) of the base (200) of each optoelectronic component (100), wherein the laser chip (400) of each optoelectronic component (100) has a second electrical contact surface (420), wherein the second electrical contact surface (420) is electrically connected by means of a second bond wire (225) to a section of the base (200) which is electrically connected to the second solder contact surface (220), wherein the optoelectronic components (100) are arranged in an electrical series circuit (630) on a surface (601) of the circuit board (600), wherein the base (200) of each optoelectronic component (100) has an approximately rectangular shape and the housings (110) of the optoelectronic components (100) are arranged close together.

This printed circuit board design device (20) is provided with: a board graph creation unit (26) that creates a board graph representing the components and connections between the components included in a designed board; a circuit block graph creation unit (28) that creates a circuit block graph representing the components and connections between the components included in a circuit block included in a new board; a subgraph extraction unit (29) that performs a search using, as a starting node, a node, which is among a plurality of nodes included in the board graph, for a component of the same type as a specific component included in the circuit block, and thereby extracts a plurality of subgraphs, each including the starting node, from the board graph; a feature extraction unit (30) that uses a trained model to extract a feature of the circuit block graph from information representing the circuit block graph and extract a feature of the subgraph from information representing the subgraph; and a similarity calculation unit (31) that calculates the similarity between the feature of the circuit block graph and the feature of each subgraph.

The invention discloses a printed circuit board design review method and device, electronic equipment and a storage medium, and relates to the technical field of printed circuit board design review, and the method comprises the steps: disassembling complex review into a plurality of calculation tasks, respectively mapping the calculation tasks to corresponding hardware acceleration modules, and carrying out the parallel processing capability, the continuous value and the probability value output by the pre-trained review model are quickly obtained, the review time is greatly shortened, and the review efficiency is improved. By means of the review model based on mass data training, design data is comprehensively and accurately analyzed, the defect that errors are prone to occurring in manual review is avoided, and review accuracy is remarkably improved. Quantized data output by the model provides a basis for judging design data quality and positioning problem types, and assists in discovering potential problems. Meanwhile, a clear examination result is output according to the model, and a problem attribute and an optimization strategy are given, so that a direction is indicated for design improvement, the manual investigation and thinking cost is reduced, and the manual and trial and error cost is effectively reduced.

The invention discloses an electronic component package automatic generation method and system based on intelligent information extraction. The method comprises the steps of obtaining an electronic component design document uploaded by a user and a processing mode instruction specified by the user; calling an optical character recognition service to recognize a specified page of the design document to obtain a recognition result containing text content and layout information; the recognition result and the processing mode instruction are input into a pre-trained large language model, so that the large language model outputs a key design parameter set related to package creation; submitting the key design parameter set to the user for interactive verification and correction to obtain final design parameters confirmed by the user; and according to the processing mode instruction, performing logic conversion processing on the final design parameter, and generating a target packaging parameter conforming to the design specification of the printed circuit board. According to the method and the system provided by the invention, the full-process automation from the unstructured document to the standardized packaging design is realized, and the design efficiency and accuracy are improved.

The present application provides a method and apparatus for placing vias on a printed circuit board. The method comprises: obtaining a first position coordinate information table including position coordinate information of multiple vias on the target printed circuit board based on a design file of the target printed circuit board; inserting the position coordinate information of a basic via before each position coordinate information in the first position coordinate information table to obtain a second position coordinate information table; wherein, in the second position coordinate information table, the i-th row is the position coordinate information of the basic via, and the i+1th row is the position coordinate information of the vias on the target printed circuit board, where i is an odd number; placing a basic via in a target drawing of the printed circuit board design software based on the position coordinate information of the basic via; and copying the position coordinates of the basic via from the i-th row to the i+1th row in the target drawing based on the second position coordinate information table. The above method can realize the automatic placement of multiple vias on the target printed circuit board.

The application relates to a PCB precision line side etching inhibition method based on vacuum etching, which comprises the following steps: acquiring line feature data from a printed circuit board design file, constructing a multi-dimensional parameter matrix containing coordinate positions and feature values; establishing a calculation model of etching liquid flow rate by using a regression analysis algorithm according to the line feature variables in the multi-dimensional parameter matrix; generating the flow rate distribution of each region through the calculation model, and adjusting the flow rate value in combination with differential control parameters; generating a flow rate control instruction sequence according to the adjusted flow rate value, driving the etching equipment to adjust the etching liquid flow rate of each nozzle; acquiring deviation data of the current flow rate and the target flow rate through real-time monitoring, adjusting the flow regulating valve to make the flow rate converge to the target range; collecting line edge shape data in the etching process, calculating the side etching degree and updating the flow rate parameters according to the result; and optimizing the regression coefficients in the calculation model by associating data, and establishing an adaptive parameter optimization mechanism.

The application relates to the field of printed circuit board computer-aided design and manufacturing technology, and discloses a printed circuit board copper conductive structure acute angle detection method and device and electronic equipment, the method comprises the following steps: acquiring two-dimensional closed graphs corresponding to each copper conductive structure existing in intersection relation on a printed circuit board; merging each two-dimensional closed graph to form a merged graph defined by a contour ring; calculating the included angle at each vertex on the contour ring of the merged graph; and detecting an acute angle with an included angle less than a preset acute angle threshold. The "hidden" acute angle newly generated after the intersection and merging of multiple copper conductive graphs, which cannot be recognized by a traditional DRC method, can be automatically and accurately detected, so that the reliability and manufacturability of printed circuit board design are effectively improved.

A header-less printed circuit board connector system (HLPCBC) comprising novel terminal connectors and printed circuit board (PCB) designs that eliminate the need to solder a stamped blade or PCB header to a PCB. The HLPCBC comprises a plurality of blade terminals formed from the PCB material extending from the PCB. The blade terminals are separated by terminal gaps. A complementary multi-blade terminal connector is used to couple with the terminal connectors. In some forms the multi-blade terminals are arranged in single or multiple planes. Metal plating can extend across the layers of blade terminals to increase strength or can be used for strain relief. The PCBs can be housed in a PCB housing having a blade support wall. The HLPCBC comprises blade terminals on one end of the PCB, whereas in other embodiments, blade terminals extend from opposed ends of the PCB.

The invention relates to the technical field of PCB design, and provides a design method and device of a multi-layer printed circuit board, electronic equipment and a storage medium. According to the method, design requirements for the multilayer printed circuit board are received through a visual control so as to generate a preset printed circuit board design document corresponding to the format of third-party software, and the printed circuit board design document comprises lamination information of the multilayer printed circuit board; identifying the printed circuit board design document line by line to obtain lamination information corresponding to each line; adding the lamination information corresponding to each row into an initial lamination information file corresponding to the printed circuit board design software to obtain a target lamination information file; and importing the target lamination information file into the printed circuit board design software to complete the design of the multi-layer printed circuit board. According to the application, the lamination information of the printed circuit board design document is identified, so that the printed circuit board design text is quickly converted into the target lamination information file which can be identified by the printed circuit board design software.

The application provides a kind of medium-high voltage printed circuit board and its insulation strengthening method, it is related to printed circuit board insulation design technical field, the method is based on the initial structure data between positive direct current terminal pad and negative direct current terminal pad, obtains first insulation strengthening data;Based on the initial structure data between direct current pad and system midpoint potential conductor, obtains second insulation strengthening data;Based on the initial structure data at the capacitor terminal pad, obtains third insulation strengthening data;Based on the initial structure data of hole array area, the method of adding the shielding layer extending radially outside under the hole array area is used to obtain fourth insulation strengthening data;Based on first insulation strengthening data, second insulation strengthening data, third insulation strengthening data and fourth insulation strengthening data, the method of adding the outermost layer of insulation material to printed circuit board is used to obtain insulation strengthening result.The application solves the problems of high cost and poor insulation performance of the existing printed circuit board design method.

The invention relates to the technical field of printed circuit board design, and discloses a DRC result visualization method and device oriented to PCB design and electronic equipment. The method comprises the following steps: when performing DRC result visual rendering, acquiring a priority value and a violation type identifier of each violation item for at least two DRC violation items at the same coordinate position in the same physical layer; a superposition rendering layer stack is constructed based on the priority values, rendering layers are distributed for the violation items, and the higher the priority is, the higher the sequence of the layers is; for each violation item, acquiring a visual presentation parameter based on the violation type identifier of the violation item, and forming a graphic element on the corresponding rendering layer; and performing synthesis rendering on the superposition rendering layer stack to generate a DRC fusion visual identifier which is associated with the coordinate position and fuses each graphic element. According to the invention, refined and prioritized visual fusion and presentation of multiple violation information at the same coordinate position are realized, and the auditing efficiency and accuracy of high-density PCB design are improved.