17 results about "White-box testing" patented technology

The invention provides a ChatGPT-based security protection software rule generation method and system, and relates to the field of network security threat detection, and the specific scheme is as follows: automatically crawling a threat analysis report A of an effective rule generated by other security equipment platforms, taking the effective rule of the threat analysis report A as a rule case to carry out instruction fine tuning on ChatGPT, and taking the effective rule of the ChatGPT as a rule case; generating and obtaining a sample fine tuning GPT model; obtaining a threat analysis report B of the security equipment to be protected, initiating a request for ChatGPT based on the sample fine tuning GPT model, analyzing the threat analysis report B by ChatGPT according to the request to generate a threat detection rule, and converting the threat detection rule into a grammar rule of security protection software; and performing simulation attack test and white-box test based on the grammar rules, and screening out grammar rules which do not pass the test to obtain general grammar rules of the security protection software. According to the method, the problem that the attack response is slow in the prior art is solved, the threat detection rule is automatically designed and generated, and the use cost is reduced.

The invention discloses a white box test method and device, a storage medium and computer equipment. Relates to the technical field of software testing, the financial field and the medical field. The technical problem that an existing white box testing method is low in efficiency is mainly solved. The method mainly comprises the steps that historical test coverage information and an incremental function of a to-be-tested version source code are pulled, and the historical test coverage information is determined based on a test coverage rate merging result of a previous version source code of the to-be-tested version source code; respectively generating a function call relation graph and a function control flow chart of the incremental function; screening the incremental function according to the historical test coverage information, the function call relation graph and the function control flow chart, and creating a test case according to a screening result; and executing the test case to perform white-box test on the source code of the version to be tested, and generating a test result of the source code of the version to be tested. The method is mainly used for white-box testing.

The invention discloses an AI-driven full-scene intelligent test platform which comprises the following steps: performing static scanning on a target code under the triggering of a code submission event through a code static scanning module to generate a scanning result, and then inputting the scanning result into a pre-trained first AI model to obtain code quality evaluation data. And generating a white box test case through a white box case generation module. In addition, a black box test case is generated through a black box case generation module. An automatic script generation module inputs the black box test case into a pre-trained fourth AI model to generate an automatic test script; and finally, running the white box test case and the automatic test script to obtain an original test report. And inputting the original test report into a pre-trained fifth AI model through a result analysis module, and generating defect distribution data and test suggestion data. The full-scene test coverage of the software life cycle is realized, the test of each link of the software is comprehensively and systematically covered, and the test efficiency is improved.

The invention discloses a device with fault diagnosis and positioning functions, a design method, a medium and equipment, and the design method comprises the steps: determining a function which needs to be realized by the device, and designing a function module; determining a fault diagnosis and positioning scheme for functional modules and selected devices of the device, and designing a fault diagnosis and positioning mechanism; designing a security assurance module; and packaging the device into a finished product. And carrying out white-box test, function test, acceleration test and type test test on the finished product of the device, feeding back the test result of each test under the condition that all the tests are not passed, and optimizing the next round of iteration until all the tests are passed. According to the method, the PFMEA analysis in the production process is introduced, the traditional method that fault diagnosis is only based on DFMEA analysis in the design stage is broken, the offering of the safety red line of the rail transit product is practiced, the safety of equipment is ensured, and the method has great practicability.

An asset risk assessment method and device based on simulated penetration attacks and white-box testing. The method includes: conducting simulated penetration attacks on the agreed scope and targets from the perspective of an attacker; collecting associated asset information on the attack link and restoring the attacker's attack link; continuously performing white-box testing on each node on the attack link and visualizing the full-link attack process; constructing a security analysis view to quantify and evaluate risks for multiple types of assets. The present invention uses continuous white-box testing for monitoring and analysis, changing the known threat convergence from passive to active, so as to continuously and effectively handle risks, thereby raising the attack threshold and shortening the repair window period.

Training and / or utilization of machine learning model(s) (e.g., neural network model(s)) in automatically generating test case(s) for source code. Techniques disclosed herein can be utilized in generating test case(s) for unit test testing (or other white-box testing) and / or for functional testing (or other black-box testing).

An apparatus having fault diagnosis and localization functions and a design method therefor, and a computer-readable storage medium and an electronic device. The design method comprises: determining functions that an apparatus is required to implement, and designing functional modules; determining fault diagnosis and localization schemes for the functional modules of the apparatus and selected components, and designing fault diagnosis and localization mechanisms; designing a safety assurance module; packaging the apparatus into a finished product; and performing white-box testing, functional testing, acceleration testing and type testing on the finished apparatus product; and when the finished apparatus product fails to pass all tests, separately feeding back test results of the tests, and performing optimization and the next round of iteration until the finished apparatus product passes all the tests. By means of introducing PFMEA into a production process, conventional fault diagnosis methods simply based on DFMEA at a design stage are overcome, thereby ensuring the safety of devices.

The application relates to the technical field of current fault prediction, in particular to an ANN chip current fault prediction algorithm based on near-field scanning, which is realized based on a near-field scanning system and characterized by the following steps: white-box testing and analysis model, current estimation principle, construction and training of an artificial neural network model, and fault detection application. The current estimation method of the application is applied to fault detection of a power supply network, the current distribution of the power supply network is estimated by solving a quadratic programming problem, the current flow direction, the conductor current amplitude and the via current amplitude are respectively obtained, the differences of the estimated current distribution with defects are detected, the positions of the coaxial via defects and the significant decrease of the current amplitude of the open circuit are detected, and the open circuit problems existing in the coaxial via or the circuit can be clearly detected through the application.

The application provides a rule generation method and system of a ChatGPT-based security protection software, and relates to the field of network security threat detection, and the specific scheme is as follows: a threat analysis report A of an effective rule generated by other security device platforms is automatically crawled, the effective rule of the threat analysis report A is used as a rule case to instruct the fine tuning of ChatGPT, and a sample fine-tuned GPT model is generated; a threat analysis report B of a security device to be protected is acquired, a request is initiated to ChatGPT based on the sample fine-tuned GPT model, ChatGPT generates a threat detection rule according to the request by analyzing the threat analysis report B, and the threat detection rule is converted into a syntax rule of a security protection software; simulation attack testing and white box testing are performed based on the syntax rule, syntax rules that do not pass the testing are filtered out, and a general syntax rule of the security protection software is obtained. The application improves the problem that the prior art responds to attacks slowly, and automatically designs and generates a threat detection rule, thereby reducing the use cost.

The application relates to the technical field of vehicles, in particular to a method and device for detecting information security production consistency of a vehicle and electronic equipment, wherein the method comprises the following steps: receiving a target component injected with first key information, and performing black box testing on the target component to obtain a black box testing result; if the black box testing result meets first preset testing conditions, performing white box testing on the target component to generate a white box testing result of the target component; and if the white box testing result meets second preset conditions, generating security testing information of the target component. Thus, the method can verify whether a debugging port of a component is effectively closed, thereby guaranteeing the production consistency of the information security of the component.

The invention relates to the technical field of software testing, and provides a YOLO-based interface recognition and automatic testing method in a multi-system environment, which comprises the following steps of: performing recognition detection on a test software interface screenshot obtained through desktop screenshots by utilizing a pre-trained YOLO model; an RPA or ADB tool is adopted to realize automatic operation; performing a black box test, and verifying whether output results of the YOLO model under various inputs conform to expectation from the perspective of a user without paying attention to internal implementation details of a tool; carrying out white-box testing, and carrying out fine-grained testing on the YOLO model, the RPA operation script and the ADB tool command; and compiling a test script, and automatically executing identification and operation test. Through efficient and accurate recognition, powerful automatic operation, excellent real-time performance and a reliable exception handling mechanism, the software testing efficiency and accuracy are remarkably improved, and the method has wide application prospects and important technical value.

A method for assessing test adequacy of deep neural networks based on element decomposition is provided. The network testing is divided into black box testing and white box testing, of which key elements are decomposed and defined. Network parameters including a weight matrix and a bias vector are extracted. Importance values of neurons in individual layers of the deep neural network are calculated and clustered, and an importance value hot map of neurons in each layer is generated based on clustering results. Mutation testing, and index calculation and evaluation are performed.

The invention discloses a distributed credential and credential privacy computing system, which belongs to the technical field of credential and credential security and comprises a security isolation module for dividing the privacy computing system into a data layer, a computing layer and an application layer which are isolated and communicated through an API (Application Program Interface) and an encryption protocol; the cloud side end collaborative operation framework bears operation penetrating through the privacy computing system, and the cloud center management node, the edge node and the credential desktop client cooperatively execute a distributed privacy computing task; the communication management module monitors a connection health state in real time and realizes fault self-recovery of a communication link by adopting a main and standby socket switching strategy; and the verification platform is used for testing and verifying the intelligent calculation algorithm, the communication logic and the system flow which are about to be executed or are being executed in a simulation environment based on a white-box test method. According to the method, on the premise that data privacy security is guaranteed, distributed computing power is fully utilized, complex intelligent tasks are stably and reliably completed, and continuous optimization can be achieved.

The invention discloses a chip testing method and device, equipment and a medium, and relates to the technical field of chip testing. The method comprises the following steps: building a chip firmware white-box test platform on a simulation platform, and registering at least one debugging tool chain through a preset standardized interface; executing the test case on the white-box test platform to obtain a basic test log, and triggering the debugging tool chain to synchronously collect multi-dimensional operation data in the execution process of the test case; and performing format unification and time axis alignment processing on the multi-source log data to generate standardized time axis data, performing association analysis on the standardized time axis data based on a preset association analysis algorithm, identifying abnormal behaviors and potential risks in the test process of the chip firmware, and displaying a corresponding analysis result through a visual interface. Through the technical scheme of the invention, the problems caused by difficulty in positioning probability problems, tool chain splitting and insufficient collaboration in a chip testing process can be solved.

The invention discloses a white-box test instrumentation method based on macro control, which constructs a stub code fusion management mechanism, fuses stub codes and macro definition into a header file, realizes standardization and structuring of the stub codes, provides a basis for subsequent stub code structured generation, automatic execution and stub code removal, and improves the efficiency of stub test. Standardized instrumentation positions and unified code styles are adopted, stub codes written by different testers can be standardized, the stub codes are integrated together in a macro definition mode, a mechanism that code macro definition is expanded in a pre-compiling stage is introduced, a standardized stub code template is combined, and the pre-compiling efficiency is improved. According to the method, pre-compiling processing is uniformly carried out on instrumentation codes in the compiling process, the stub codes are automatically executed in combination with the characteristics of Boolean variables, removal of the stub codes and closing of the stub codes in a test header file are supported through macro definition and the switching characteristics of the Boolean variables, and normal operation of a program is not affected in the process.

The application discloses a hardware white box test combination device and a test method thereof, and relates to the technical field of hardware white box testing.The test station module of the device comprises a computer, a top test area, a bottom test area and a high-voltage test area.The computer is used for managing traceability files and executing test procedures.A network switch comprises a plurality of network ports, and each network port is connected to other modules through a cable.The network switch is used for providing network communication for a printer, the test station module, an electronic tool cabinet and a test cabinet module.The printer is used for printing test cases.The electronic tool cabinet module is used for storing test tools.The test cabinet module comprises a digital multimeter, an oscilloscope, a camera, a high-voltage tester, a program-controlled power supply, a hygrothermograph, a code scanning gun, a probe, a mechanical arm, a rack and a cabinet body, and is used for providing a hardware white box test environment for a module to be tested.Based on the device, the test cost of the hardware white box can be reduced.

The invention discloses a hardware white box test combination device and a test method thereof, and relates to the technical field of hardware white box test, and a test station module in the device comprises a computer, a top layer test area, a bottom layer test area and a high voltage test area; the computer is used for managing traceability files and executing a test process; the network switch comprises a plurality of network ports; each network port is connected with other modules through a cable; the network switch is used for providing network communication for the printer, the test station module, the electronic tool cabinet and the test cabinet module; the printer is used for printing a test case; the electronic tool cabinet module is used for storing test tools; the test cabinet module comprises a digital multimeter, an oscilloscope, a camera, a high-voltage tester, a programmable power supply, a hygrothermograph, a code scanning gun, a probe pen, a mechanical arm, a rack and a cabinet body, and the test cabinet module is used for providing a hardware white-box test environment for the tested module. Test is carried out based on the device, and the test cost of the hardware white box can be reduced.