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Method for charging fee for use of network resources and method and system for allotting network resources

When an internet service provider (ISP) 1 charges web site (web site) proprietors A, B and C a fee for using their desired basic network capacity from the network resources thereof, the ISP 1 give one web site proprietor (e.g. A) a preferential option enabling one web site proprietor terminal to temporarily use a part of the basic network resources or its entirety thereof allotted to the other web site proprietor terminals (e.g. B and C) as well as a non-preferential option enabling the other web site proprietor terminals to temporarily use a part of the basic network resources or its entirety thereof allotted to the one web site proprietor terminal, and the ISP 1 charges web site proprietors the fee for their use of the basic network capacity at a premium rate/discount rate in correspondence with their purchased preferential option/non-preferential option. Accordingly, with the purchase of preferential option/non-preferential option, the basic network capacity may be substantially increased or decreased, so that the effective use of the digital network is facilitated and also, the fee for the use of the basic network capacity is made reasonable with adoption of the premium rate/discount rate in correspondence with the preferential option/non-preferential option.
Owner:OKI ELECTRIC IND CO LTD

Semiconductor device

In an operation to supply an input signal IN having an amplitude equal to a first power-supply voltage VDD1 to the gate of a PMOS transistor PM51 operating at a second power-supply voltage VDD2 higher than the first power-supply voltage VDD1, the levels of signals are converted by using PMOS transistors PM1 to PM4. The sources of the PMOS transistors PM1 and PM3 are connected to a line of the first power-supply voltage VDD1 whereas the sources of the PMOS transistors PM2 and PM4 are connected to a line of the second power-supply voltage VDD2. The gate of the PMOS transistor PM4 is connected to the drains of the PMOS transistors PM1 and PM2. The gate of the PMOS transistor PM2 is connected to the drains of the PMOS transistors PM3 and PM4. An inverted signal of the input signal IN is supplied to the gate of the PMOS transistor PM1 and the input signal IN is supplied to the gate of the PMOS transistor PM2. The amplitude of the input signal IN is converted from a magnitude equal to a difference between a reference signal VSS and the first power-supply voltage VDD1 into a magnitude equal to a difference between the first power-supply voltage VDD1 and the second power-supply voltage VDD2. A signal obtained as a result of the conversion is output from the PMOS transistors PM1 and PM2, being used for controlling electrical conduction of a PMOS transistor PM51.
Owner:SOCIONEXT INC
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