The invention provides a high-speed lossless 
data compression system based on a 
content addressable memory, which relates to the technical field of the 
data compression of a hardware 
system. The invention solves the problems of low compression rate, heavy consumption of limited RAM resources in a hardware 
chip, indefinite search cycle, and the like, and solves the problem that address conflict exists in the dictionary searching which is realized by adopting a 
hash table address module. The invention comprises a 
clock module, an input 
data buffer module, a dictionary module, an LZW 
algorithm kernel module and an output encoding module, wherein, the dictionary module is constructed by the 
CAM inside an FPGA, the bit width of the 
CAM is 17, and the depth of the 
CAM is 512; the address of thememory in the CAM corresponds to the code of the LZW 
algorithm in the LZW 
algorithm kernel module, and the memory comprises a 
comparator and a trigger; the trigger is used for storing data, and the 
comparator is used for comparing input data with the data in the trigger and outputting a matching 
signal. The 
data compression system realizes the high-speed lossless data compression based on the FPGAand enlarges the range of application.