A
comparator circuit (5) comprising a fully differential main
amplifier unit (10, 10b). The main
amplifier unit (10, 10b) comprises a control port and is adapted to control a bias current of a first
branch of the main
amplifier unit (10, 10b) and / or a bias current of a second
branch of the main amplifier unit (10, 10b) in response to one or more control voltages supplied to the control port of the main amplifier unit (10, 10b). The
comparator circuit (5) comprises circuitry (60) for balancing the voltages at the positive and negative input terminals (12a, 12b) of the main amplifier unit (10, 10b) during a first
clock phase of the
comparator circuit (5). Furthermore, the comparator circuit (10, 10a) comprises a switched-
capacitor accumulator unit with a differential input. The switched-
capacitor accumulator unit is operatively connected to the positive and negative output terminals (14a, 14b) of the main amplifier unit (10, 10b) for sampling voltages at the positive and negative output terminals (14a, 14b) of the main amplifier unit (10, 10b) during the first
clock phase, and operatively connected to the control port of the main amplifier unit (10, 10b) for supplying said one or more control voltages.