32 results about "Half-integer" patented technology

When detecting light scattered by an object to be inspected by using a pulse laser as a light source, noise increases unless a sampling repletion period of an A / D converter is determined so as to be related to a pulse oscillation repetition period of the light source. (1) The sampling repletion period of the A / D converter is set equal to the pulse oscillation repetition period of the light source or an integer times thereof, and the sampling is synchronized with oscillation of the light source. Or (2) the sampling repletion period of the A / D converter is set equal to a half-integer times the pulse oscillation repetition period of the light source. Even if a ripple component resulting from emission pulses of the light source remains in the scattered light signal supplied to the A / D converter remains, therefore, its influence can be eliminated or reduced.

A interferometer type polarization beam combiner and splitter, which can combine or split polarized light over a wide band, is provided. The interferometer type polarization beam combiner and splitter includes: an optical splitter; an optical coupler; an optical path length difference imparting unit, which includes a plurality of optical waveguides arranged between the optical splitting unit and the optical coupling unit; one or two input / output ports connected to the optical splitter; and two input / output ports connected to the optical coupler. A half-integer of a wavelength of λc is set as a normalized phase difference, for the optical path length difference imparting unit, between two polarization states, and means for generating a difference in refractive index dispersion is provided between the optical waveguides of the optical path length difference imparting unit, so that the change rate of the transmittance with respect to wavelength is suppressed for the two polarization states.

A fractional-N frequency divider includes a half-integer frequency divider and a duty cycle adjustment circuit. The half-integer frequency divider includes a multi-modulus divider containing a cascaded chain of div2 / 3 cells, which is responsive to a multi-bit modulus control signal, and a phase control circuit configured support half-integer frequency division by the multi-modulus divider, by providing an input terminal of the multi-modulus divider with a periodically phase-flipped input signal having a first frequency. The duty-cycle adjustment circuit is configured to generate a divider output signal with a 50% duty cycle in response to a periodic signal generated by the half-integer frequency divider.

A magnetic resonance detection apparatus is provided that is not susceptible to acoustic ringing, and a method is provided for eliminating or canceling acoustic ringing from a detected magnetic resonance signal. Specifically, a composite pulse is utilized that allows for both efficient reduction of acoustic ringing signals and the detection of true NQR signals. The composite pulse can be used in any of the common NQR pulse sequences currently utilized simply via substitution of the original single pulses with the composite pulse. Furthermore, although a preferred application involves the spin-1 nucleus .sup.14N and NQR, the composite pulse will be useful for the NQR of other nuclei such as .sup.35CI and .sup.39K and in NMR applications and involving half-integer quadrupolar nuclei and spin- 1 / 2 nuclei. In addition, coil ringdown and piezoelectric ringing are also substantially reduced.

An apparatus and a method for producing a multi-pulse sequence for irradiating a substance provided with quadrupole nuclei with either integer or half-integer spins to detect an NQR signal emitted therefrom. The apparatus has pulse sequence generating means adapted to produce a combination of two or more pulse sequences, arranged so that a definite regularity of the phase alteration of pulses in each of the pulse sequences occurs that is equivalent to a shift of spectral components of the pulse sequences in relation to each other. Furthermore, in at least one of the pulse sequences, there are not less than two phases alternating. A preparatory pulse may be included in one of the pulse sequences to reduce the effect of temperature, increase the intensity of the NQR signal and simultaneously eliminate intensity anomalies. Alternatively, the combination of pulse sequences may be different from a combination of PAPS and NPAPS, and none of the pulse sequences contain a preparatory pulse.

In order to prevent accumulation of rounding errors caused by the integer-based bilinear interpolation used in the motion compensation process of image coding and decoding methods, two types of P frames are used for unidirectional motion compensation prediction, namely: P+ frames, which round the results of bilinear interpolation with real number operations to the nearest integer and rounds half integer values (0.5 added to an integer) away from zero, and P- frames, which differs from P+ frames in that the above mentioned half integer values are rounded towards zero. Utilising both of these P+ and P- frames enables cancelling of rounding errors and prevents the accumulation of rounding errors.

A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ).

The present invention concerns the enhancement of critical current densities in cuprate superconductors. Such enhancement of critical current densities include using wave function symmetry and restricting movement of Abrikosov (A) vortices, Josephson (J) vortices, or Abrikosov-Josephson (A-J) vortices by using the half integer vortices associated with d-wave symmetry present in the grain boundary.

In order to prevent accumulation of rounding errors caused by the integer-based bilinear interpolation used in the motion compensation process of image coding and decoding methods, two types of P frames are used for unidirectional motion compensation prediction, namely: P+ frames, which round the results of bilinear interpolation with real number operations to the nearest integer and rounds half integer values (0.5 added to an integer) away from zero, and P- frames, which differs from P+ frames in that the above mentioned half integer values are rounded towards zero. Utilising both of these P+ and P- frames enables cancelling of rounding errors and prevents the accumulation of rounding errors.

The invention belongs to the technical field of frequency dividers of integrated circuits, and particularly provides an integer and half-integer frequency divider based on characteristic state feedback. The frequency divider comprises a clock phase inverter, an N-bit binary counter, an output clock selector and a feedback controller; and the feedback controller comprises a level type characteristic state decoder, a triggering type characteristic state decoder, a level type inverter and a triggering type inverter. According to the frequency divider, by feeding back characteristic states determined by a frequency division coefficient and conducting phase processing on an input clock, the binary counter is triggered at the edge designated by a to-be-divided clock, and the counting bit corresponding to the frequency division coefficient is selected and output to serve as a frequency division clock; and only an interface signal of the binary counter needs to be processed, the internal structure of the binary counter does not need to be changed, the advantages of being simple in design and high in universality are achieved, and not only can complete integer and semi-integer frequency division be achieved, but also the duty ratio of the frequency division clock can be adjusted by taking a 0.5 input clock cycle as the precision.