41 results about "Process control monitoring" patented technology

A test structure for use in a semiconductor chip. In a preferred embodiment, a number of die are formed in an array on a semiconductor wafer substrate. Each die includes an active area defined by a seal ring and is separated from those adjacent to it by a thin scribe line. In addition to the operational structures formed in the active area of each die, one or more test structures are formed. In a preferred embodiment, these test structures are formed into one or more PCM (process control monitor) test pattern layout areas that are positioned near the seal ring and outside of the operational bond pads. Some or all of individual pads in the PCM test pattern layout area may then be connected to corresponding features on adjacent dice, and in some applications enable the simultaneous performance of WAT (wafer acceptance test) and CP (circuit probe) testing.

A process control monitoring system for a process control plant uses graphic trend symbols to assist in detecting and monitoring trends of process variables within the process control plant. A graphic display application within the process control monitoring system may implement and display each graphic trend symbol to graphically indicate or encapsulate current trend and value information of a process variable within the process control plant. The graphic display application may display the graphic trend symbol in a spatially realistic location within a graphical representation of the process control plant while maintaining the hierarchical structure or each hierarchical level of the process plant. The graphic display application may also include a zoom feature that enables a user to quickly drill down through tend data to obtain more information and to support problem identification and diagnosis tasks.

A process control monitoring system for a process control plant uses graphic trend symbols to assist in detecting and monitoring trends of process variables within the process control plant. A graphic display application within the process control monitoring system may implement and display each graphic trend symbol to graphically indicate or encapsulate current trend and value information of a process variable within the process control plant. The graphic display application may display the graphic trend symbol in a spatially realistic location within a graphical representation of the process control plant while maintaining the hierarchical structure or each hierarchical level of the process plant. The graphic display application may also include a navigation pane and a zoom feature that enable a user to quickly drill down through tend data to obtain more information and to support problem identification and diagnosis tasks.

A process control monitoring system for a process control plant uses graphic trend symbols to assist in detecting and monitoring trends of process variables within the process control plant. A graphic display application within the process control monitoring system may implement and display each graphic trend symbol to graphically indicate or encapsulate current trend and value information of a process variable within the process control plant. The graphic display application may display the graphic trend symbol in a spatially realistic location within a graphical representation of the process control plant while maintaining the hierarchical structure or each hierarchical level of the process plant. The graphic display application may also include a navigation pane and a zoom feature that enable a user to quickly drill down through tend data to obtain more information and to support problem identification and diagnosis tasks.

Process control monitors are disclosed that are produced using at least some of the same process steps used to manufacture a MEMS device. Analysis of the process control monitors can provide information regarding properties of the MEMS device and components or sub-components in the device. This information can be used to identify errors in processing or to optimize the MEMS device. In some embodiments, analysis of the process control monitors may utilize optical measurements.

A method to remove the silicon nitride capacitor dielectric layer from over the poly-1 layer on portions of the wafer including non-capacitor areas such as the pad contact area, process control monitor (PCM) testsite areas and scribe line areas. By removing the silicon nitride, H2 can penetrate to the polysilicon and thereby increase the uniformity of the VT. In a first embodiment of the invention, the silicon nitride capacitor dielectric layer is etched away from over the poly-1 layer in the pad area. The removal of the SiN layer allows H2 to penetrate into the poly-1 layer and improve the threshold voltage (VT). Uniformity of long channel VT-N was improved when we modify the pad struture of PCM to increase the clear out ratio of capacitor Si3N4 to 1.0584%. In a second embodiment of the invention, the silicon nitride capacitor dielectric is etched away from over the poly-1 layer in the process control monitor (PCM) testsite area between the chips. In a third embodiment of the invention, the silicon nitride capacitor dielectric is etched away from over the poly-1 layer in the scribe area between the between the chips.

An interconnect structure includes: a plurality of dielectric layers having aligned process control monitor (PCM) pads, and a conductive structure above a topmost one of the PCM pads. The conductive structure electrically connects the topmost PCM pad to a device under test above a level of the topmost PCM pad. The conductive structure is sized and shaped so as to leave a majority portion of the topmost PCM pad exposed for access by a test probe.

Process control monitors are disclosed that are produced using at least some of the same process steps used to manufacture a MEMS device. Analysis of the process control monitors can provide information regarding properties of the MEMS device and components or sub-components in the device. This information can be used to identify errors in processing or to optimize the MEMS device. In some embodiments, analysis of the process control monitors may utilize optical measurements.

The systems and methods described provide improved process control operating range and capabilities and integrate process control monitoring and management with broader process automation (PA) systems process management, extending the real-time operation and control of a process control system to process handling of a PA system, and extending PA-style process management by adding real-time process controls and monitoring, and adding new functionality by permitting management of these processes to externally defined completion goals. This combination provides new functionality in dynamically determined process flexibility, extended operating range and extended process recipe definition capabilities for process control systems using this technology, and provides improved error recovery and exception handling of traditional PA systems.

The invention provides a method for manufacturing a fuse trimming chip. The method comprises the steps of: acquiring a plurality of test fuse trimming chips capable of representing a fuse trimming chip to be trimmed; applying a different trimming voltage to each test fuse trimming chip, determining whether each test fuse trimming chip is successfully trimmed, and acquiring the lowest trimming voltage for successful trimming; based on the nominal trimming voltage of the fuse trimming chip to be trimmed and the lowest trimming voltage, acquiring the maximum fluctuation range of the resistance ofthe fuse trimming chip to be trimmed; and performing process control monitoring so that the actual fluctuation range of the resistance of the fuse trimming chip to be trimmed is within the maximum fluctuation range. The method can calculate the maximum fluctuation range allowed by the resistance of the fuse trimming chip to be trimmed with process fluctuation, so that the actual fluctuation rangeof the resistance of the fuse trimming chip to be trimmed can be within the maximum allowable fluctuation range through process control monitoring, and the fuse trimming reliability is improved.

The invention discloses a BCB thickness on-chip monitoring and control method and device. The method comprises the following steps: preparing a monitoring graph on an epitaxial wafer; spin-coating thesurface of a substrate with BCB glue and heating the BCB glue for curing; testing the thickness of the BCB layer by adopting a micro-area reflection interference method; and etching the BCB layer byadopting a dry etching process, and repeatedly testing the BCB thickness of the monitoring area. According to the monitoring method, the BCB thicknesses of different areas on the wafer can be rapidlyobtained, and the surface of the wafer cannot be damaged. The method can be used for a BCB planarization process of an InP HBT device, on-chip real-time monitoring of the BCB thickness can be achieved, and the production efficiency is effectively improved. Process control monitoring is carried out by setting a specific monitoring graph, real-time monitoring of the BCB thicknesses of different areas is achieved, and the process control capacity is effectively improved.

A process control monitoring system for a process control plant uses graphic trend symbols to assist in detecting and monitoring trends of process variables within the process control plant. A graphic display application within the process control monitoring system may implement and display each graphic trend symbol to graphically indicate or encapsulate current trend and value information of a process variable within the process control plant. The graphic display application may display the graphic trend symbol in a spatially realistic location within a graphical representation of the process control plant while maintaining the hierarchical structure or each hierarchical level of the process plant. The graphic display application may also include a zoom feature that enables a user to quickly drill down through tend data to obtain more information and to support problem identification and diagnosis tasks.

The embodiment of the invention discloses a wafer process fault prediction method and device, electronic equipment and a storage medium. The method comprises the following steps: determining a detection parameter matrix according to detection parameters fed back by a process control monitoring unit; inputting the detection parameter matrix into a process fault prediction model; and obtaining a prediction result matrix output by the process fault prediction model. The wafer comprises a device placing area, the center of the device placing area, the vertex of an internally tangent N-polygon of the device placing area and the midpoint of the connecting line of the vertex and the center are used as reference points, the wafer further comprises a plurality of photomask areas, and the photomask areas where the reference points are located are provided with process control monitoring units; the prediction result matrix comprises a plurality of first elements, the preparation process of the wafer comprises a plurality of process steps, and different first elements are used for representing the probability of faults in different process steps. According to the technical scheme provided by the embodiment of the invention, the wafer detection time can be shortened, and the process fault prediction of each process step in the wafer preparation process can be realized.

A circuit unit structure for process monitoring, especially a circuit unit structure applied to advance integrated circuit processing for integrated circuit testing and process monitoring, compared with conventional circuit unit structure, comprises a plurality of pore chains, a floating metal layer and an arc-shaped connection part, and is capable of notably reducing point discharge and radio frequency coupling or crosstalk effect during interflow or radio frequency testing processes, and preventing a too huge parasitic capacitance Cp from existing among the pore chains, thereby preventing assessment errors of via-hole resistance values from occurring, and further promoting reliability degree of the overall integrated circuit processing and testing.

A process control monitoring method uses a navigation pane for navigating within a graphical depiction of a process control plant. The navigation pane that includes a unit selection area and an equipment selection area, wherein (i) the unit selection area includes one or more unit selector icons that correspond to one or more units in the graphical depiction of the process control plant, (ii) the equipment selection area includes one or more equipment selector icons that correspond to one or more equipment in the graphical depiction of the process control plant, (iii) each unit in the process control plant includes one or more equipment in the process control plant, and (iv)each unit selector icon is associated with one or more equipment items selector icons based on the included one or more equipment in the process control plant associated with the unit that corresponds to the unit selector icon. In response to receiving a selection of a first unit selector icon, one or more equipment selector icons in the equipment area associated with a first unit in the process control plant that corresponds to the selected first unit selector icon are displayed, wherein (i) the one or more equipment selector icons associated with the selected first unit selector icon are displayed in the equipment selection area and (ii) the one or more non-selected unit selector icons remain displayed in the unit selection area. Moreover, one or more equipment in the graphical depiction of the process control corresponding to the first unit selector icon is displayed.

The invention provides a process control monitoring method of nanocrystalline deposition density, a module thereof and a manufacturing method thereof. The process control monitoring module comprises a first module and a second module which are formed on a semiconductor substrate. The first module comprises a bottom oxide layer, a nanocrystalline layer, a top oxide layer and a polysilicon layer from the bottom up. The second module comprises a top oxide layer and a polysilicon layer from the bottom up. Through testing the capacitance of the first module and the second module of the process control monitoring module, the density of deposited nanocrystalline can be obtained, thus process stability in a nanocrystalline deposition process can be monitored, and abnormal condition of nanocrystalline particle deposition process can be fed back timely.