30results about How to "High speed readout" patented technology

Dummy cells in an erased state and in a write state are used to generate a dummy current corresponding to the average current of currents flowing in the dummy cells using a 1 / 2 current generating circuit, and the dummy current is compared with a current corresponding to a memory cell current flowing in a selected normal cell using a current sense amplification circuit to generate internal read data according to a result of the comparison. With such a configuration, a non-volatile semiconductor memory device capable of reading data at high speed can be achieved.

A nonvolatile memory device includes: a first reference cell; a second reference cell; a circuit that generates a first mirror current proportional to a current flowing through the first reference cell; a circuit that generates a second mirror current proportional to a current flowing through the second reference cell; a sense amplifier that reads out data by comparing a current flowing through a memory cell with a reference current; and a selection circuit that sets a selection state of the first reference cell and the second reference cell such that, in a readout mode, the reference current is generated based on at least the first mirror current, and in a verify mode, the reference current is generated based on the second mirror current.

A high-speed, high-resolution column A / D converter having a noise reduction function to eliminate a fixed pattern noise etc. is provided with a small circuit scale. Each column A / D converter includes a dual-output D / A converter for selecting two reference voltages from among a reference voltage group supplied in common to each column A / D converter, so as to output the two reference voltages to sandwich each sensor signal voltage input to each column A / D converter, along with a charge-redistribution D / A converter having a full scale determined by the above two reference voltages. Thus, the high-speed, high-resolution column A / D converter is achieved with a small circuit scale. Further, by the utilization of high-speed conversion capability, noise reduction is performed through digital calculation after the A / D conversion.

Two bias circuits (20) which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element (21a, 21b) between a power supply node Vcc and a junction node (Nca, Ncb), where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element (22a, 22b) between the power supply node and an output node (Nouta, Noutb), where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element (23a, 23b) and a fourth active element (24a, 24b) between the junction node and a current supply node Nsa (Nsb) and between the output node and the current supply node, respectively, where a bias voltage is adjusted.

By first readout, the current input from a selected cell 13 is converted by a preamplifier 3 and a VCO 4 into pulses of a frequency inversely proportionate to the current value, and the number of the pulses within a preset time interval is counted by a counter 5 so as to be stored in a readout value register 6. A selected cell is then written to one of two storage states, and second readout is then carried out. The storage state of the selected cell is verified by comparing a count value of the counter for the second readout, a count value for the first readout as stored in a readout value register and a reference value stored in a reference value register 7 to one another. By the use of the VCO, the integrating capacitor for the current or reference pulse generating means, so far needed, may be eliminated to assure a small area, low power consumption and fast readout.

The invention provides a flash memory comprising a memory array comprising a memory mat MAT-0, MAT-1; a page buffer 170-0, holding data read from the memory mat MAT-0; a page buffer 170-1, holding data read from the memory mat MAT-1; an ECC circuit 140, performing data error checking and correction; an output buffer 110 for outputting data; and a transferring control element, controlling transferring of data between the page buffer 170-0, page buffer 170-1, ECC circuit 140 and output buffer 110. When the memory mat MAT-0 is selected, the transferring control element transfers data held by thepage buffer 170-0 to the page buffer 170-1 of the memory mat MAT-1.

A solid-state imaging device includes: a pixel section wherein pixels including photoelectric conversion devices are arranged in a matrix; and a pixel driving section including a row selection circuit which controls the pixels to perform an electronic shutter operation and readout of the pixel section. The row selection circuit has a function of selecting a readout row from which a signal is read out and a shutter row on which reset is performed by discharging charge accumulated in the photoelectric conversion devices, in accordance with address and control signals. The row selection circuit can set, in accordance with the address and control signals, in the pixels of the selected row, at least a readout state, a discharge state where a smaller amount of the charge accumulated in the photoelectric conversion devices than the reset is discharged, an electronic shutter state, and a charge state where the charge is accumulated in the photoelectric conversion devices.

It is possible to rapidly create frame data used when moving a spatial light modulation element in a scan direction and forming an image by inputting the frame data into a spatial light modulation element in accordance with the movement in the scan direction. There is provided a method for creating the frame data used when moving the spatial light modulation element having a plurality of arranged plotting element groups in the scan direction defining an inclination angle against the arrangement direction of the plotting element groups and inputting the frame data into the spatial light modulation element to form an image in accordance with the movement. The frame data creation method creates frame data according to image data in which pixel data are two-dimensionally arranged in a sub-scan direction corresponding to the aforementioned scan direction and a main scan direction orthogonal to the sub-scan direction. The image data is subjected to deformation processing sot that the image data corresponding to the plotting element groups (circle 1 to circle 6) are arranged in the main scan direction and the frame data is created in accordance with the deformed image data.

An imaging apparatus including a ramp voltage generation circuit having a first period for outputting an offset voltage that sets a reference voltage for the comparator circuit, and a second period for outputting a reference voltage having a slope-shaped voltage waveform that varies with time, wherein the generation circuit has a first drive state in which a voltage change amount per unit time of the reference voltage in the second period is a first voltage amount, and a second drive state in which the voltage change amount per unit time of the reference voltage in the second period is a second voltage amount that is less than the first voltage amount, and wherein the offset voltage in the second drive state is less than a value obtained by multiplying the offset voltage in the first drive state by a ratio of the second voltage amount to the first voltage amount.

When the variable resistance nonvolatile memory element having a first electrode, a second electrode, and a transition metal oxide layer sandwiched between the first electrode and the second electrode is in an initial state, the first electrode A first forming voltage is applied between the first electrode and the second electrode until the first formation of the first operable state reversibly transitioned between the high resistance state and the low resistance state occurs, between the first electrode and the second electrode. Applying a second forming voltage between the second electrodes until it changes to a resistance value lower than the resistance value of the low resistance state in the first operable state after the first formation. Formation of the variable resistance nonvolatile memory element proceeds until the second formation of the second operable state of the resistance state is performed.

The invention provides a debugging and display controlling system of a radar information processor. The debugging and display controlling system comprises a high-speed data transmission module, a display control module and a resident monitoring module, wherein the resident monitoring module is mounted on the radar information processor; the display control module is used for receiving external input task requirements and sending corresponding control commands, the control commands are transmitted to the resident monitoring module through the high-speed data transmission module, and the resident monitoring module responds to the control commands, carries out corresponding operations on the radar information processor and uploads operation results to the display control module through the high-speed data transmission module. According to the debugging and display controlling system, the coherence debugging and display controlling for the radar information processor can be realized, the real-time performance and coherence of the radar information processor are verified, and the test efficiency of the radar information processor is increased.

At the start of a volume comprising a magnetic tape, a start volume label including volume identifying information is provided. After the start volume label, a batch file, which is the data body, is provided. At the end of the volume, an end volume label having the same contents as those of the start volume label is provided. When the volume is mounted, one of the start and end volume labels, which is the closer one to the seek position, is read. When the volume is unmounted and when the seek position is the end of the data, the end volume label is additionally written. Since the volume label is written at the two places, the mounting operation is speedily carried out, and the reliability of media is enhanced.

In an image capturing apparatus having an image sensor including a plurality of unit pixels each having a plurality of photoelectric conversion portions and a microlens, the image sensor can be scanned with a first scan method of adding and reading out signals from a portion of the photoelectric conversion portions by a predetermined number of unit pixels and with a second scan method of adding and reading out signals from the photoelectric conversion portions by the predetermined number of unit pixels. A pixel signal read out with the second scan method is selected if a defocus amount is larger than a threshold value and the larger of the pixel signal read out with the second scan method and a signal obtained by using the pixel signal read out with the first scan method is selected if the defocus amount is equal to the threshold value or less.

The invention discloses a multifunctional photosensitive synapse device based on a two-dimensional material and a preparation method thereof, the device comprises a substrate, a grid electrode, a source electrode, a drain electrode and a stacking structure, the grid electrode, the source electrode, the drain electrode and the stacking structure are arranged on the substrate, the stacking structure comprises a first two-dimensional material layer, a second two-dimensional material layer and a third two-dimensional material layer, the grid electrode is arranged on the substrate, and the third two-dimensional material layer is arranged on the substrate. A first two-dimensional material layer, a second two-dimensional material layer and a third two-dimensional material layer are sequentially covered on the grid electrode, a source electrode and a drain electrode are respectively covered on the third two-dimensional material layer, and a channel is formed between the source electrode and the drain electrode. The second two-dimensional material layer comprises hexagonal boron nitride in a defect state, the first two-dimensional material layer serves as a light absorption layer, the second two-dimensional material layer serves as an isolation layer, and the third two-dimensional material layer serves as a readout layer. The device is simple in structure, simple and understandable in working principle, simple in preparation process and easy to master; based on vertical stacking of pure two-dimensional thin film materials, the size is small, and the requirements for high density and high integration level are met.

The invention relates to a quick read out system and a method of holographic data storage, belonging to the optical storage technical field. The quick read out method is as follows: firstly, a plurality of holograms are recorded at intervals on a holographic medium; then, the high-speed read out of the holograms is realized by means of the synchronous working among precise addressing equipment, an electro-optical switch and high-speed image collection equipment in the state of high-speed motion of the holographic medium. Because the quick read out system of holographic data storage is designed by the method, and consists of a microdrive positioning controller, a pulse generator, high-speed precise addressing equipment, an electro-optical switch, high-speed image collection equipment, a laser and a necessary optical element, the holographic medium is in a high-speed motion state all the time during continuously reading out a plurality of holograms, thereby realizing continuous high-speed read out of the holograms.

The present invention provides a non-volatile semiconductor memory device, comprising: a memory array, including memory pads (MAT-0, MAT-1); a page buffer (170-0), which maintains the The data out; Page buffer (170-1), keeps the data read from storage pad (MAT-1); ECC circuit (140), carries out error detection and correction of data; Output buffer (110), outputs data and a forwarding control section, controlling data forwarding between the page buffer (170-0), the page buffer (170-1), the ECC circuit (140), and the output buffer (110). When the memory mat (MAT-0) is selected, the transfer control unit transfers the data held in the page buffer (170-0) to the page buffer (170-1) of the memory mat (MAT-1).

Provided are an imaging element capable of not only reducing noise such as shading but also executing high-speed pixel read-out, a method for controlling same, and a camera. In a three-transistor-driven pixel circuit (11), the drain of a reset transistor (113) is connected to a drive signal line DRNL (n), and the drain of an amplification transistor (114) is connected to a power supply voltage VDD. A row drive circuit (12a) rapidly switches the level of voltage to be applied to the drive signal line DRNL (n) from a high-level voltage VH to a lowest-level voltage VLL and slowly restores the voltage level from the lowest-level voltage VLL to the original high-level voltage VH through a low-level voltage VL.

Before each content file is recorded first to a recording medium, a flag indicating a recording state of a content file is generated corresponding to a physical area where an index file can be continuously recorded. An index file is generated which associates attribute information with the generated flag added thereto with real data of each content file, and the generated index file is recorded to the recording medium. Since fragmentation of the physical area where the index file is recorded is restrained to a minimum level, a high-speed reading operation is realized.

An imaging apparatus including a ramp voltage generation circuit having a first period for outputting an offset voltage that sets a reference voltage for the comparator circuit, and a second period for outputting a reference voltage having a slope-shaped voltage waveform that varies with time, wherein the generation circuit has a first drive state in which a voltage change amount per unit time of the reference voltage in the second period is a first voltage amount, and a second drive state in which the voltage change amount per unit time of the reference voltage in the second period is a second voltage amount that is less than the first voltage amount, and wherein the offset voltage in the second drive state is less than a value obtained by multiplying the offset voltage in the first drive state by a ratio of the second voltage amount to the first voltage amount.

Dummy cells in an erased state and in a write state are used to generate a dummy current corresponding to the average current of currents flowing in the dummy cells using a 1 / 2 current generating circuit, and the dummy current is compared with a current corresponding to a memory cell current flowing in a selected normal cell using a current sense amplification circuit to generate internal read data according to a result of the comparison. With such a configuration, a non-volatile semiconductor memory device capable of reading data at high speed can be achieved.

A semiconductor device and a read method of a NAND flash memory capable of performing high-speed read or high-reliability read are provided. The read method of a NAND flash memory includes: a pre-charging step of pre-charging a sensing node via a voltage-supply node; a discharging step of discharging a voltage of the sensing node to the voltage-supply node to perform a prescribed operation; a recharging step of recharging the sensing node via the voltage-supply node after the prescribed operation; and a read step of discharging a NAND string and performing sensing of a memory cell.