35results about How to "Reduce data dependence" patented technology

A memory device includes a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform coarse decoding and fine decoding. In coarse decoding, the decoder decodes in parallel two or more codewords, which share a common block of bits, to determine error information. Next, the decoder corrects errors in a first codeword based on the error information. Then, it is determined if the shared common block of data bits is corrected. If the shared common data block is updated, then error correction based on the error information is prohibited in codewords sharing the common block of data bits with the first codeword. In fine decoding, a single codeword is decoded at a time for error correction.

A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, and each data block having a number of data bits. The decoding apparatus is configured to decode, in parallel, a first codeword with one or more other codewords to determine error information associated with each codeword. For errors in a common data block shared between two codewords being decoded in parallel, the error information includes a data block identifier and associated error bit patterns. Further, the decoding apparatus is configured to update the codewords based on the error information.

The present invention is related to a digital circuit for use in a mixed-signal circuit. The digital circuit comprises:a first circuit for direct digital synthesis comprising a first phase generator (PG1) arranged for being fed with a phase generator input signal, a first phase-to-amplitude converter (PAC1) arranged for being fed with a phase from the first phase generator and for generating a first carrier wave output, and first signal combining means (R1) for combining the first carrier wave output with a first input signal,a noise generator (NG) arranged for generating a pseudo-random noise signal,combining means (S) for combining the pseudo-random noise signal and the phase generator input signal such that the phase generator input signal to the first phase generator (PG1) is randomised,a second circuit for direct digital synthesis comprising a second phase generator (PG2) arranged for being fed with the pseudo-random noise signal, a second phase-to-amplitude converter (PAC2) arranged for being fed with a phase from the second phase generator and for generating a second carrier wave output, and second signal combining means (R2) for combining the second carrier wave output with a second input signal, whereby the second carrier wave output combined with the second input signal is comprised in the first input signal.