45 results about "10G-EPON" patented technology

The invention discloses a timing device and method for automatically capturing a 10G EPON (10 Giga Ethernet Passive Optical Network) message and relates to the field of communication. The timing method comprises the following steps: after starting the automatic capturing, counting for a preset time by an absolute clock subjected to time correction of a user / OLT (Optical Line Terminal) / ONU (Optical Network Unit) under an absolute timing capturing mode; starting the 10G EPON message capturing and writing into a capturing cache according to screening conditions; under a relative timing capturing mode, detecting a frame content and a frame state captured by specific starting; starting to count by a timing clock till reaching the time preset by the user; and starting a packet grabbing process and writing into the capturing cache according to screening conditions. According to the timing method provided by the invention, the 10G EPON message can be automatically and accurately captured and analyzed; the space for storing the captured message is reduced by designing accurate timing and filtering conditions; the performance and the use efficiency of a remote dispatcher are promoted; and the intercommunication capacity of different equipment factories is enhanced.

The invention discloses a method for judging the optimum working voltage of an avalanche photodiode APD of 10G EPON, comprising the following steps: S1: Obtaining the reverse breakdown voltage V of the APD according to the test data of BOSA or the RSSI under the condition of no light br ;S2: Set an initial working bias voltage, select a fixed input optical power, test the current bit error rate or number of bit errors according to the preset duration, and then increase the working bias step by step with the set step value and repeat Test, test at least 3 points until the bit error rate or the number of bit errors increases; S3: Set the working bias as x and the bit error rate as y, and solve the quadratic equation y=ax 2 +bx+c, get a, b, c three coefficients; S4: According to the obtained a, b, c three coefficients, calculate the extreme value to get the corresponding APD DAC; S5: use the APD DAC value for sensitivity test, if qualified If passed, the APD DAC at the current temperature is subtracted from the corresponding temperature value in the APD DAC LUK table and updated to the APDDAC LUK after translation. If it fails, it fails.

Embodiments of the invention relate to a velocity detection method and a device, wherein the method comprises the following steps: filtering received signals to obtain a frequency component; comparing the frequency component with a threshold value, and outputting a velocity indicating signal according to the comparison result. The device comprises a filter processing module which is used for filtering the received signals to obtaining the frequency component; a comparison module which is used for comparing the frequency component with the threshold value; and a velocity judging logic module which is used for outputting the velocity indicating signal according to the comparison result. The embodiments perform filtering process to the received signals according to spectral distribution characteristics of the received signals so as to obtain the frequency component, and compare the frequency component with the threshold value so as to determine the velocity indicating signal. The velocity detection method and the device are suitable for the synchronous lead code re-defined by the 10G EPON standard.

The invention relates to a hardware coding method and circuit based on FEC (forward error correction) in a 10G EPON ONU (Ethernet passive optical network optical network unit). The hardware coding method comprises the following steps: S10. writing 66bit-wide data sent by a scrambler part into an fifo buffer; S20. writing the rest 65bit-wide data into nine register arrays in sequence after taking out the 66bit-wide data from the fifo buffer and removing the LSB (least significant bit) each time; S30. instantly starting a corresponding Reed-Solomon (RS) (252, 220) coder for coding once data are written into a certain register array, and then writing check bytes obtained through coding into corresponding bits of the corresponding register arrays to be registered; and S40. reading the data from the register arrays according to a certain format, thus obtaining the FEC coded data. The method and the circuit have the following advantages: the method is simple, convenient and effective and has high operability; and the circuit has a smaller scale and can achieve higher hardware circuit time sequence speed.

The invention discloses a 10G EPON OLT (Ethernet passive optical network optical line terminal) single-fiber three-dimensional optical module comprising a 10Gb / s laser driver, a 1.25Gb / s laser driver, a microcontroller, a single-fiber three-dimensional optical device and a received signal strength indication circuit under a burst mode, wherein the 10Gb / s laser driver and the 1.25Gb / s laser driver are respectively connected with an XFP (10 gigabit small form factor pluggable) connector and provide an automatic optical-power control (APC) loop and a backlight current sampling function; an analog quantity is converted into a digital quantity reported to the microcontroller; the microcontroller controls to continuously light; and optical power sent by different ONUs (optical network units) is monitored by receiving terminal sudden optical power monitoring, thereby realizing that a plurality of EPON ONU optical signals are subjected to time division multiplexing on the same optical fiber so as to realize single-fiber three-dimensional data transmission.

The invention discloses a capturing circuit and a writing control method of 10G EPON (10 Giga Ethernet Passive Optical Network) messages. The writing control method comprises the following steps: receiving EPON messages interacting among 10G EPON OLT (Optical Line Terminal) and ONU (Optical Network Unit) through an optical module and a 10G SERDES (Serializer / Deserializer); combining and triggering message capturing according to set conditions after the decoding at a PCS (Physical Coding Sub-layer); writing the captured message into capturing cache, wherein the steps and formats for storing the capturing frames are as follows: writing 128bit frame data at an even number clock period while a frame envelope is valid; and writing the frame head byte number, the frame end byte number, the reaching time, the frame error indication, CRC (Cyclic Redundancy Check) verification error indication and frame boundary symbol of the frame within a clock period at the frame end. With the adoption of the capturing circuit and the writing control method, continuous EPON messages of 10 G can be captured and analyzed rapidly and precisely; the storage space of the captured message is reduced through specific triggering and screening conditions; the performance and the use efficiency of the remote scheduling are improved; and the inter-compatibility of factories of different equipment is enhanced.