This invention discloses a high-efficiency task
scheduling system for heterogeneous multi-core on-
chip networks based on a multi-armed
slot machine, relating to the field of task scheduling in heterogeneous multi-core systems. It addresses the problem of high
power consumption in existing scheduling technologies by proposing this solution. During runtime, the following scheduling steps are periodically executed using time slices as the cycle: S1. Status acquisition of the underlying hardware platform and upper-layer application load; S2. Time and
power consumption estimation based on on-
chip network prediction; S3. Calculation of priority index and net
gain; S4. Allocation of heterogeneous cores based on integer
linear programming; S5. Runtime closed-loop feedback and control parameter updates. The
advantage is that when the scheduler calculates the net
gain, it imposes a strong mathematical penalty on applications with high
packet injection rates that excessively distribute core allocation. This forces the
system to perceive NoC traffic hotspots during runtime and intelligently converge applications with high communication demands to core configurations that are physically closer. This avoids problems such as
virtual channel deadlock and
bus congestion in NoC routers.