173 results about "Verification problem" patented technology

A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist, which can be analyzed by standard verification tools and by other tools that operate on netlists. The correctness of such systems can require reasoning about a much smaller number of memory entries than exist in the circuit design, and by abstracting such memories to a smaller number of entries, the computational complexity of the verification problem is substantially reduced.

The “identity authentication program” (IAP) creates a custom set of authentication questions in response to a user request to have a user password reset. The IAP accesses a record located in a data source containing information related to the user's recent computer activity and generates an authentication question and a corresponding answer based on the record. In order to reset a user password, the user must correctly answer a designated number of questions from the custom set of authentication questions. In a preferred embodiment, the IAP bases authentication questions on recent e-mail messages sent by the user. Because the questions are generated at the time of the user's request, the answers are unique and can not be memorized. Because the questions are based on recent activities of the user, the questions are hard to guess by an unauthorized person.

The invention provides a multithreaded program output uniqueness detection and evidence generation method based on program constraint building. The output uniqueness verification problem is converted into a constraint solving problem by building a constraint expression according to the multithreaded program semanteme, a constraint solver is used for detecting whether different outputs are present and counter-example execution paths explaining different outputs are generated; the multithreaded program output uniqueness detection and evidence generation method comprises the steps of firstly, carrying out the instrumentation of the detected program, executing the program and obtaining an execution path, secondly, converting the execution path into a quantifier-free first-order logic expression covering all feasible thread interleaving according to the multithreaded program execution semanteme, thirdly, building a uniqueness verification condition aiming at the output result of once operation, and finally, verifying whether one path is present so that the output value is inconsistent with the operation result by use of the constraint solver. The method is capable of detecting whether the output of the multithreaded program is unique under given input; in case of non-uniqueness of the outputs, a counter-example sequence is shown to explain the trigger process of the non-uniqueness.

A customer satisfaction system, includes a query module for automatically sending queries to customers as to problems with goods or services provided by a provider according to a predetermined schedule and for receiving responses from customers to the queries; an analysis module for analyzing responses from customers and for sending responses indicating a problem to a problem solver for resolution; and at least one problem solver for responding to customer problems, for generating solutions to customer problems and for transmitting solutions to customers; wherein, upon transmission of a solution to a customer problem to a customer, the query module sends a query to the customer requesting verification that the problem has been solved.

A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist by replacing memory with substitute nodes representing selected slots in the memory, segmenting word level nodes, including one or more of the substitute nodes, in the netlist into segmented nodes, finding reduced safe sizes for the segmented nodes and generating an updated data structure representing the circuit design using the reduced safe sizes of the segmented nodes. The correctness of such systems can require reasoning about a much smaller number of memory entries and using nodes having smaller bit widths than exist in the circuit design. As a result, the computational complexity of the verification problem is substantially reduced.