120results about "Error correction/detection using arithmatic codes" patented technology

An electronic data storage device having a Reed Solomon (RS) decoder including a syndrome calculator block responsive to information including data and overhead and operative to generate a syndrome, in accordance with an embodiment of the present invention. The electronic data storage device further includes a root finder block coupled to receive said syndrome and operative to generate at least two roots, said RS decoder for processing said two roots to generate at least one error address identifying a location in said data wherein said error lies; and an erasure syndrome calculator block responsive to said information and operative to generate an erasure syndrome, said RS decoder responsive to said information identifying a disk crash, said RS decoder for processing said erasure syndrome to generate an erasure error to recover the data in said disk crash.

Method and apparatus for image transmission using arithmetic coding, based on continuous error detection uses a controlled amount of added redundancy. A continuous error detection scheme is provided, wherein there is a trade-off between the amount of added redundancy and the time needed to detect an error once it occurs. Herein, there is no need for the cyclic redundancy check (CRC) to wait until an entire block of data has been received and processed before an error can be detected. The invention can be used to great advantage both in the automatic repeat request (ARQ) and other concatenated coding schemes. Errors in the received bit stream are detected by introducing added redundancy, e.g., a forbidden symbol, in the arithmetic coding operation. The forbidden symbol is never intended to be encoded. The redundancy error causes loss of synchronization, which is used to detect errors. If a forbidden symbol gets decoded, it means that an error has occurred. In this invention, there is direct control over the amount of redundancy added vs. the amount of time it takes to detect an error. For image compression systems, by using the invention and ARQ, only one device would suffice both for source compression and channel coding.

Methods, apparatus and systems for error correction of n-valued symbols in codewords of p n-valued symbols with n>2 and for n=2 and k information symbols have been disclosed. Coders and decoders using a Linear Feedback Shift Registers (LFSR) are applied to generate codewords and detect the presence of errors. An LFSR can be in Fibonacci or Galois configuration. Errors can be corrected by execution of an n-valued expression in a deterministic non-iterative way. Deterministic error correction methods based on known symbols in error are provided. Corrected codewords can be identified by comparison with received codewords in error. N-valued LFSR based pseudo-noise generators and methods to determine if an LFSR is appropriate for generating error correcting codes are also disclosed. Methods and apparatus applying error free assumed windows and error assumed windows are disclosed. Systems using the error correcting methods, including communication systems and data storage systems are also provided.

An encoding apparatus and an encoding method, a decoding apparatus and a decoding method, a recording medium, and a program suitable for encoding image signals with a higher compression ratio for transmission or accumulation. In an arithmetic coding section, from among the syntax elements of input image compression information, the frame / field flag is first encoded by a frame / field flag context model. When the macroblock to be processed is subjected to frame-based encoding, a frame-based context model, specified in the current H.26L standard, is applied. On the other hand, when the macroblock to be processed is subjected to field-based encoding, a field-based context model is applied for the syntax elements described below. The present invention is applied to an encoder for encoding image information and a decoder for decoding image information.

An encoding apparatus and an encoding method, a decoding apparatus and a decoding method, a recording medium, and a program suitable for encoding image signals with a higher compression ratio for transmission or accumulation. In an arithmetic coding section, from among the syntax elements of input image compression information, the frame / field flag is first encoded by a frame / field flag context model. When the macroblock to be processed is subjected to frame-based encoding, a frame-based context model, specified in the current H.26L standard, is applied. On the other hand, when the macroblock to be processed is subjected to field-based encoding, a field-based context model is applied for the syntax elements described below. The present invention is applied to an encoder for encoding image information and a decoder for decoding image information.

A Golay-code generator configured for generating Golay complementary code pairs comprises a sequence of delay elements configured for providing a predetermined set of fixed delays to at least a first input signal and a sequence of adaptable seed vector insertion elements configured for multiplying at least a second input signal by a variable seed vector, wherein each of a plurality of seed vectors corresponds to at least one predetermined piconet. The Golay-code generator may further comprise multiplexers configured for switching inputs and outputs of at least two delay elements in the sequence of delay elements to produce a plurality of compatible delay vectors. The Golay-code generator may further comprise a code-truncation module configured to shorten the Golay complementary code pairs for producing a plurality of daughter codes. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

A memory read-channel is provided with selective transmission of error correction data. The disclosed read-channel improves throughput and reduces power consumption when error correction codes are unnecessary. The data read from a memory device comprises user data, error detection data and error correction data. In one embodiment, the error detection data is evaluated to determine if there is a data error; and the error correction data is transmitted only if a data error is detected. In another variation, the error detection data is evaluated during data transmission to determine if there is a data error and the transmission is suspended if a data error is detected. Typically, the error detection data comprises a cyclic redundancy check and the error correction data comprises parity check data.

Methods and apparatuses for performing arithmetic encoding and / or decoding are disclosed. In one embodiment, an arithmetic decoder comprises a sequencer to generate a context identifier for an event of an event sequence, a probability estimator to determine a value for a LPS and a probability estimate for the LPS, and a decoding engine that includes a range register to assign a value to a range for the LPS. The value is based on the probability estimate, a value stored in the range register and the context identifier to a range for the LPS if the context identifier is not equal to an index and the value is not based on the value stored in range register if the context identifier is equal to the index. The decoding engine further determines a value of a binary event based on the value of the range for the LPS and bits from an information sequence.

A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and / or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.

Methods and apparatuses for performing arithmetic encoding and / or decoding are disclosed. In one embodiment, an arithmetic decoder comprises a sequencer to generate a context identifier for an event of an event sequence, a probability estimator to determine a value for a LPS and a probability estimate for the LPS, and a decoding engine that includes a range register to assign a value to a range for the LPS. The value is based on the probability estimate, a value stored in the range register and the context identifier to a range for the LPS if the context identifier is not equal to an index and the value is not based on the value stored in range register if the context identifier is equal to the index. The decoding engine further determines a value of a binary event based on the value of the range for the LPS and bits from an information sequence.

According to one embodiment, an error correction encoding apparatus includes a linear encoder and a low-density parity check (LDPC) encoder. The linear encoder supports a linear coding scheme enabling a parity check to be carried out by a division using a generating polynomial and applies the generating polynomial to input data to obtain linear coded data. The LDPC encoder applies a generator matrix corresponding to a parity check matrix for an LDPC code to the linear coded data to obtain output data. The parity check matrix satisfies Expression (1) shown in the specification.

A decoder, an encoder, a decoding method and an encoding method are provided. The encoding method includes receiving data; generating a set of first codewords by applying a first encoding process on the received data; and performing a second encoding process on a folded version of each first codeword to provide a set of second codewords, wherein a folded version of a first codeword is representative of a storage of the first codeword in a two dimensional memory space, wherein the second codeword comprises redundancy bits.