30 results about "Platinum silicide" patented technology

The method of manufacturing the semiconductor device comprises forming a transistor including a gate electrode and a source / drain diffused layer over a semiconductor substrate, forming a nickel platinum film over the semiconductor substrate, covering the gate electrode and the source / drain diffused layer, making a first thermal processing to react the nickel platinum film with the source / drain diffused layer to form a nickel platinum silicide film, and removing an unreacted part of the nickel platinum film using a chemical liquid of 71° C. or more containing hydrogen peroxide.

A substrate having at least one silicon device is provided. A nickel platinum alloy layer is formed on the substrate. A rapid thermal process is performed to react the nickel platinum alloy layer with the silicon device to produce a nickel platinum silicide. A passivation layer is formed on the nickel platinum silicide followed by using a solution consisting of nitric acid and hydrochloric acid to remove unreacted portions of the nickel platinum alloy layer.

The present invention provides a method of manufacturing a semiconductor device, comprising forming an electrode pattern made of silicon on a gate insulating film in an n-MOS region and a p-MOS region of a semiconductor substrate, masking the n-MOS region including the first electrode pattern with a first insulating film pattern, forming a first metal film made of platinum all over the surface, forming a gate electrode consisting of a platinum silicide in the p-MOS region, forming an silicon oxide film on the surface of the gate electrode by oxidation, dissolving away a non-reacting Pt film, removing the first insulating film pattern, masking the p-MOS region including the electrode pattern with a second insulating film pattern, forming a second metal film made of europium all over the surface, and forming a gate electrode consisting of a europium silicide in the n-MOS region.

Tips including a platinum silicide at an apex of a single crystal silicon tip are provided herein. Also, techniques for creating a tip are provided. The techniques include depositing an amount of platinum (Pt) on a single crystal silicon tip, annealing the platinum and single crystal silicon tip to form a platinum silicide, and selectively etching the platinum with respect to the formed platinum silicide.

Tips including a platinum silicide at an apex of a single crystal silicon tip are provided herein. Also, techniques for creating a tip are provided. The techniques include depositing an amount of platinum (Pt) on a single crystal silicon tip, annealing the platinum and single crystal silicon tip to form a platinum silicide, and selectively etching the platinum with respect to the formed platinum silicide.

The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.

Described herein is a semiconductor structure and method of manufacture. The semiconductor structure includes a plurality of semiconductor fins on a substrate and a plurality of raised active regions, wherein each raised active region is located on sidewalls of a corresponding semiconductor fin among said plurality of semiconductor fins. The raised active regions are laterally spaced from any other of the raised active regions. Each raised active region comprises angled sidewall surfaces that are not parallel or perpendicular to a topmost horizontal surface of said substrate. The raised active regions are silicon germanium (SiGe). The semiconductor structure includes a metal semiconductor alloy region contacting at least said angled sidewall surfaces of at least two adjacent raised active regions. The semiconductor alloy region includes a material selected from the group consisting of nickel silicide, nickel-platinum silicide and cobalt silicide.

A technique capable of reducing threshold voltage and reducing high-temperature heat treatment after forming a gate electrode is provided. An n-type MIS transistor or a p-type MIS transistor is formed on an active region isolated by an element isolation region of a semiconductor substrate. In the n-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a hafnium silicide film. On the other hand, in the p-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a platinum silicide film. Also, the gate electrodes are formed after the activation annealing (heat treatment) for activating impurities implanted into a source region and a drain region.

A method of fabricating a metal silicide layer over a substrate is provided. First, a hard mask layer is formed over a gate formed on a substrate and a portion of the substrate is exposed. Thereafter, a first metal silicide layer, which is a cobalt silicide or a titanium silicide layer, is formed on the exposed substrate. After that, the hard mask layer is removed and a second metal silicide layer is formed over the gate, wherein a material of the second metal silicide layer is selected from a group consisting of nickel silicide, platinum silicide, palladium silicide and nickel alloy. Since different metal silicide layers are formed on the substrate and the gate, the problem of having a high resistance in lines with a narrow line width and the problem of nickel silicide forming spikes and pipelines in the source region and the drain region are improved.

To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source / drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source / drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.

A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.

Described herein is a semiconductor structure and method of manufacture. The semiconductor structure includes a plurality of semiconductor fins on a substrate and a plurality of raised active regions, wherein each raised active region is located on sidewalls of a corresponding semiconductor fin among said plurality of semiconductor fins. The raised active regions are laterally spaced from any other of the raised active regions. Each raised active region comprises angled sidewall surfaces that are not parallel or perpendicular to a topmost horizontal surface of said substrate. The raised active regions are silicon germanium (SiGe). The semiconductor structure includes a metal semiconductor alloy region contacting at least said angled sidewall surfaces of at least two adjacent raised active regions. The semiconductor alloy region includes a material selected from the group consisting of nickel silicide, nickel-platinum silicide and cobalt silicide.

Provided is a technical window method for removing unreacted nickel-platinum silicide in an increased wet method. The method comprises the steps that S1) certain amount of nickel and platinum alloy is removed from an NH4OH and H2O2 mixed solution SC-1 at 70 DEG C or hydrochloric acid (HCL) at normal temperature for the first time; S2) residual nickel and platinum alloy is completely removed from an NH4OH and H2O2 mixed solution SPM at 130 to 200 DEG C; and S3) cleaning is carried out in the NH4OH and H2O2 mixed solution SC-1. According to the method, certain amount of nickel and platinum alloy is removed from the NH4OH and H2O2 mixed solution SC-1 at 70 DEG C or hydrochloric acid (HCL) at normal temperature for the first time; the residual nickel and platinum alloy is completely removed from the NH4OH and H2O2 mixed solution SPM at 130 to 200 DEG C due to the fact that proper excessive etching is carried out due to the excellent selectivity ratio of SPM to the nickel-platinum alloy; and thus, a technical window can be etched in the increased wet method.

The invention relates to a self-aligned light angle sensor using thin metal silicide anodes. Aspects of the embodiments are directed to non-contact systems, methods and devices for optical detection of objects in space at precise angles. This method involves the design and fabrication of photodiode arrays for measuring angular response using self-aligned Schottky platinum silicide (PtSi) PIN photodiodes (PN-diodes with an intrinsic layer sandwiched in between) that provide linear angular measurements from incident light in multiple dimensions. A self-aligned device is defined as one in which is not sensitive to photomask layer registrations. This design eliminates device offset between "left" and right" channels for normal incident light as compared to more conventional PIN diode constructions.

A platinum-platinum silicide modified silicon composite tip apex, and a method for forming the aforesaid tip apex are disclosed, where a metallic precursor solution and a silicon probe are reacted to form a local platinum nano-structure, which could be precisely controlled with local selectivity, and a local platinum silicide layer is formed between the platinum nano-structure and the silicon probe with an atmospheric microwave annealing (a-MWA) process conducted as well, largely enhancing the conductivity of the tip and spatial resolution of the field detection in field sensitive scanning probe microscopy. In addition to exemption from a stray-field effect and thus having better image quality, the platinum silicide-containing probe could more efficiently enhance the interfacial electron transfer efficiency as compared to the probe tip having only a platinum nano-structure, so that the probe could be applicable to a controlled conductive probe having high spatial resolution.

A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source / drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source / drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source / drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source / drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes.

A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.