25 results about "Wafer bow" patented technology

The invention relates to a method for controlling the bending degree of a silicon wafer through thinning, which is used for analyzing substrates and epitaxy with different epitaxy specifications and determining the Bow optimization trend of the substrates, namely, the epitaxy changes backwards in the positive direction or the negative direction. By selecting the thinning machine table and the thinning grinding wheel, the front face and the back face are thinned respectively, and geometric parameters of the silicon wafers can be accurately adjusted in batches. It is ensured that the influence or change trend of a subsequent film forming or thermal resume process on the Bow value meets the expectation, and deterioration of geometric parameters is reduced. In addition, Bow adjustment of a single wafer can be achieved, the bending degree of the adjusted silicon wafer is accurately controlled by adjusting machining parameters of thinning equipment, then the bending degree is matched with epitaxial machining conditions, and the epitaxial wafer is made to be qualified or meet preset requirements.

Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude. As such, trenches with high aspect ratio separate features, such that each feature includes the multi-layered epitaxial stack containing the MDI film disposed between the top and bottom FET modules.

Methods, apparatus, and computer programs for simulating back-side layer deposition are provided. Deposition of back-side layer stacks can mitigate wafer warping variations in orthogonal directions. Each of the back-side layers can be deposited using a back-side deposition apparatus.

Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude. As such, trenches with high aspect ratio separate features, such that each feature includes the multi-layered epitaxial stack containing the MDI film disposed between the top and bottom FET modules.

The application provides a method for improving wafer warping, a substrate with trenches and a deposition machine. The substrate is provided with a hard mask layer, and the substrate is placed in a process chamber of the deposition machine. The temperature in the process chamber is adjusted to a first temperature, and then a first thin film layer filling the trenches is deposited on the substrate. The temperature in the process chamber is increased to a second temperature, and then a second thin film layer is deposited on the first thin film layer. The application deposits a gate layer with a certain thickness at a low temperature to fill the trenches, and then the remaining thickness of the gate layer is deposited by increasing the temperature of the furnace tube. The application improves the warping of SGT products and improves the production capacity.

Techniques for characterizing wafer bow are provided. In some embodiments, a method for determining wafer bow characteristics may involve projecting, using a projection device disposed in or on a portion of a semiconductor fabrication chamber, one or more fringe pattern images onto a surface of a wafer. The method may further involve capturing, using one or more camera devices, images representative of reflections of the one or more fringe pattern images from the surface of the wafer. The method may further involve generating an unwrapped phase map based on the captured images. The method may further involve generating a three-dimensional reconstruction of a surface of the wafer based on the unwrapped phase map using phase-measuring deflectometry.

The application is suitable for the field of semiconductor technology, and provides a control method for wafer warpage and a substrate tray. The method comprises the following steps: placing a substrate with non-zero warpage on a substrate tray containing an air cavity; performing epitaxial layer growth on an epitaxial growth surface of the substrate by using an epitaxial process; and performing cooling treatment on the substrate and the epitaxial layer to obtain an epitaxial wafer with small warpage, wherein the air cavity of the substrate tray is shaped such that the temperature difference between the edge and the middle of the substrate tray is kept within a preset range. The application can reduce the warpage of the generated epitaxial wafer, improve the uniformity of the epitaxial wafer, and further improve the uniformity and yield of the semiconductor device prepared by using the epitaxial wafer.

The invention relates to the technical field of semiconductor detection, and provides a semiconductor wafer warping degree detection method and device, and the method comprises the steps: transmitting a laser beam to an observation window of a semiconductor equipment reaction cavity; one part of the laser is partially reflected by the observation window to form a reference reflection beam, and the other part of the laser is transmitted to the surface of a wafer in a semiconductor equipment reaction cavity and then is reflected by the surface of the wafer to form a main reflection beam; acquiring a plurality of light spots formed by the main reflection light beam and the reference reflection light beam; identifying a main light spot formed by the main reflected light beam and a reference light spot formed by the reference reflected light beam according to the motion characteristics of the plurality of light spots; compensating the displacement of the main light spot based on the displacement of the reference light spot relative to the initial reference position of the reference light spot; and calculating the warping degree of the wafer according to the compensated displacement of the main light spot. The device and the method are used for performing non-contact, online and real-time warping degree measurement on the wafer in the reaction cavity in the semiconductor technological process.

Methods, apparatus, and structures for mitigating wafer bending of a semiconductor wafer are provided herein. Deposition of the backside layer stack may mitigate wafer bending that varies in an orthogonal direction. Each backside layer may be deposited by a backside deposition device. It thus provides a substantially flat surface on the back side of the substrate.

An apparatus for measuring bow of a wafer includes a substrate holder including a support surface configured to support a wafer, and an air flow system including a plurality of air outlets in the support surface which are configured to output air for elevating the wafer above the substrate holder. A capacitor array unit including a plurality of electrodes laterally spaced from one another in the capacitor array unit, each electrode facing the support surface and being spaced a respective fixed distance from the support surface such that each electrode can form a capacitor with an opposing area of a wafer elevated by the substrate holder.

Silicon carbide (SiC) wafers and related methods are disclosed that include large diameter SiC wafers with wafer shape characteristics suitable for semiconductor manufacturing. Large diameter SiC wafers are disclosed that have reduced deformation related to stress and strain effects associated with forming such SiC wafers. As described herein, wafer shape and flatness characteristics may be improved by reducing crystallographic stress profiles during growth of SiC crystal boules or ingots. Wafer shape and flatness characteristics may also be improved after individual SiC wafers have been separated from corresponding SiC crystal boules. In this regard, SiC wafers and related methods are disclosed that include large diameter SiC wafers with suitable crystal quality and wafer shape characteristics including low values for wafer bow, warp, and thickness variation.

A plasma processing chamber for depositing a film on an underside surface of a wafer includes a showerhead susceptor. The showerhead base includes a first partition and a second partition. An upper separator fin is disposed above the top surface of the showerhead base, and a lower separator fin is disposed below the top surface of the showerhead base and aligned with the upper separator fin. The first partition is configured for depositing a first film to an underside surface of the wafer, and the second partition is configured for depositing a second film to the underside surface of the wafer. In another embodiment, the top surface of the showerhead base may be configured to receive a masking plate rather than an upper separator fin. The masking plate is provided with a first region having an opening and a masked second region. The first region is used to provide a process gas to a portion of the underside surface of the wafer for depositing a film.

Aspects of the present disclosure provide an electrostatic chuck (ESC) / backside gas (BSG) system. For example, the ESC / BSG system can include an ESC and a BSG cooling device integrated with the ESC. The ESC can be configured to generate an electrostatic chucking force according to an electrostatic voltage applied thereto to clamp a semiconductor structure with a backside placed onto the ESC. The BSG cooling device can be configured to introduce to the backside of the semiconductor structure a backside gas at a backside gas pressure. The ESC / BSG system can further include a monitoring system configured to monitoring bowing of the semiconductor structure, and a controller coupled between the monitoring system and the ESC and the BSG cooling device. The controller can be configured to adjust the electrostatic voltage and / or the backside gas pressure according to the bowing of the semiconductor structure.

A three-dimensional (3D) memory device includes a memory array device, a peripheral device, an etch stop layer, and a backside gate line slit. The memory array device includes a frontside and a backside, a plurality of memory strings, and a plurality of word lines in a staircase structure coupled to the plurality of memory strings. The peripheral device is above the frontside of the memory array device. The etch stop layer is between the memory array device and the peripheral device. The backside gate line slit extends through the backside of the memory array device to the etch stop layer. The backside gate line slit includes a conductive gate line layer and an insulating gate line layer. The 3D memory device can increase manufacturing efficiency, increase yield, reduce thermal stress, reduce fluorine contamination, increase an overlay window, and decrease overlay errors.

This invention discloses a system and operating method for reducing silicon wafer warpage in semiconductor epitaxial wafer processes, relating to the field of semiconductor technology. The invention includes a reaction chamber with a door panel hinged to its inner wall, a placement mechanism, a cleaning mechanism, and an air blowing mechanism inside the reaction chamber. By opening the door panel, the silicon wafer is placed on top of several ejector pins. During placement, the outer side of the silicon wafer presses against a placement stage, pushing a limiting plate along an axis and compressing a first spring. The reaction force of the first spring causes the placement stage to flexibly limit the silicon wafer's perimeter, preventing it from shifting in the process airflow. Subsequently, a hydraulic system is activated, causing a laser scanner to descend and perform a full-surface scan of the silicon wafer, accurately detecting warpage data. For example, when a region is detected to warp upwards by three millimeters, an external processor calculates that the corresponding ejector pin below that region needs to be lowered by two millimeters to accommodate the deformation.

Aspects of the present disclosure provide an electrostatic chuck (ESC) / backside gas (BSG) system. For example, the ESC / BSG system can include an ESC and a BSG cooling device integrated with the ESC. The ESC can be configured to generate an electrostatic chucking force according to an electrostatic voltage applied thereto to clamp a semiconductor structure with a backside placed onto the ESC. The BSG cooling device can be configured to introduce to the backside of the semiconductor structure a backside gas at a backside gas pressure. The ESC / BSG system can further include a monitoring system configured to monitoring bowing of the semiconductor structure, and a controller coupled between the monitoring system and the ESC and the BSG cooling device. The controller can be configured to adjust the electrostatic voltage and / or the backside gas pressure according to the bowing of the semiconductor structure.

The application relates to the technical field of semiconductor detection, and provides a semiconductor wafer warping degree detection method and device.The method comprises the following steps: emitting a laser beam to an observation window of a semiconductor equipment reaction cavity; making part of the laser beam partially reflect through the observation window to form a reference reflection light beam, and making another part of the laser beam transmit to the surface of a wafer in the semiconductor equipment reaction cavity, and then reflecting the wafer surface to form a main reflection light beam; acquiring a plurality of light spots formed by the main reflection light beam and the reference reflection light beam; identifying a main light spot formed by the main reflection light beam and a reference light spot formed by the reference reflection light beam according to the motion characteristics of the plurality of light spots; compensating the displacement amount of the main light spot based on the displacement amount of the reference light spot relative to the initial reference position of the reference light spot; and calculating the wafer warping degree according to the displacement amount of the compensated main light spot.The application is used for non-contact, online and real-time warping degree measurement of the wafer in the reaction cavity in the semiconductor process.

Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude. As such, trenches with high aspect ratio separate features, such that each feature includes the multi-layered epitaxial stack containing the MDI film disposed between the top and bottom FET modules.

The invention provides a wafer tray, a wafer bow adjusting method and a wafer annular defect eliminating method. The wafer tray comprises a tray body, a plurality of lifting devices and an air extractor. Wherein the disc body comprises a central supporting part and a plurality of supporting rings arranged around the central supporting part, and is used for supporting a wafer. The center of each supporting ring coincides with the center of the central supporting part, and the central supporting part and the supporting rings can move independently. The lifting device is fixedly connected with the lower side of the central supporting part or the supporting rings and used for pushing the central supporting part and the supporting rings to move in the vertical direction. An air exhaust opening of the air exhaust device is arranged below the tray body, and when the tray is used, the air exhaust device enables negative pressure to be generated below the tray body through air exhaust, so that a wafer placed above the tray body is adsorbed. According to the wafer tray, the shape of the wafer can be changed through up-down movement of the central supporting part and the supporting rings, and customization of the arch shape of the wafer is achieved.

Embodiments of the present disclosure generally relate to epitaxial film stacks and vapor deposition processes for preparing the epitaxial film stacks. In one or more embodiments, a multi-layered epitaxial stack is disposed on a substrate, and the multi-layered epitaxial stack contains a plurality of doped silicon-germanium and silicon mini-stacks. Each of the doped silicon germanium stack contains a doped-silicon-germanium layer disposed between a first silicon-germanium layer and a second silicon-germanium layer. Each of the doped-silicon-germanium layers independently contains a concentration of a dopant which may vary or be the same between each of the doped-silicon-germanium layers. The multi-layered epitaxial stack has a dopant gradient based on the concentration of the dopant within each of the doped-silicon-germanium layers such that the multi-layered epitaxial stack has a wafer bow value at a predetermined threshold. The multi-layered epitaxial stack may be used throughout the microelectronics industry.

Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to multi-layered epitaxial stacks, such as complementary field-effect-transistors (cFETs). A method is used to fabricate a layered middle dielectric isolation (MDI) structure and carbon-doping of epitaxially grown silicon germanium layers together in the cFETs. In some embodiments, by integrating the layered MDI structure together with carbon-doping of SiGe layers into the cFETs, relaxation, wafer bow, and defects in a stack have been significantly reduced when compared to traditional stacks. Advantageously, multi-layered epitaxial stacks incorporate a greater number of silicon channels (e.g., pMOS and nMOS channels) when compared to traditional stacks. Furthermore, the selectivity in the downstream processes is improved by an order of magnitude. As such, trenches with high aspect ratio separate features, such that each feature includes the multi-layered epitaxial stack containing the MDI film disposed between the top and bottom FET modules.

Embodiments of the present disclosure generally relate to epitaxial film stacks and vapor deposition processes for preparing the epitaxial film stacks. In one or more embodiments, a multi-layered epitaxial stack is disposed on a substrate, and the multilayered epitaxial stack contains a plurality of doped silicon-germanium and silicon mini-stacks. Each of the doped silicon germanium stack contains a doped-silicon- germanium layer disposed between a first silicon-germanium layer and a second silicon-germanium layer. Each of the doped-silicon-germanium layers independently contains a concentration of a dopant which may vary or be the same between each of the doped-silicon-germanium layers. The multi-layered epitaxial stack has a dopant gradient based on the concentration of the dopant within each of the doped-silicon- germanium layers such that the multi-layered epitaxial stack has a wafer bow value at a predetermined threshold. The multi-layered epitaxial stack may be used throughout the microelectronics industry.

The application provides a semiconductor device and a method for forming the same, and a method for adjusting wafer warpage. The method for adjusting wafer warpage comprises: forming a stress layer and a light-absorbing layer in contact with each other on one side of a wafer; dividing the wafer into at least one wafer part and a remaining wafer part according to warpage of the wafer in different directions, wherein warpage of the at least one wafer part is greater than that of the remaining wafer part; and irradiating a laser beam to a region of the light-absorbing layer corresponding to the at least one wafer part to reduce a difference in warpage between the at least one wafer part and the remaining wafer part.

An apparatus for measuring bow of a wafer, includes a substrate holder having a support surface configured to support a wafer; and a capacitor array unit including a plurality of electrodes laterally spaced from one another in the capacitor array unit. Each electrode faces the support surface and is spaced a respective fixed distance from the support surface such that each electrode can form a capacitor with an opposing area of a substrate provided on the support surface of the substrate holder.

Silicon carbide (SiC) wafers and related methods are disclosed that include large diameter SiC wafers with wafer shape characteristics suitable for semiconductor manufacturing. Large diameter SiC wafers are disclosed that have reduced deformation related to stress and strain effects associated with forming such SiC wafers. As described herein, wafer shape and flatness characteristics may be improved by reducing crystallographic stress profiles during growth of SiC crystal boules or ingots. Wafer shape and flatness characteristics may also be improved after individual SiC wafers have been separated from corresponding SiC crystal boules. In this regard, SiC wafers and related methods are disclosed that include large diameter SiC wafers with suitable crystal quality and wafer shape characteristics including low values for wafer bow, warp, and thickness variation.