32 results about "Wafer bow" patented technology

A set of VCSEL fabrication methods has been invented which enhance the performance and long time reliability of VCSEL devices and arrays of devices. Wafer bow caused by growing a large number of epitaxial layers required to fabricate VCSEL device generates strain and results in bowing/warping of the device wafer. The stress so generated is eliminated by applying a stress compensation layer on the substrate to a surface opposite to the epitaxial layer surface. New oxidation equipment designs and process parameters are described which produce more precision apertures and reduce stress in the VCSEL device. An ultrathin fabrication procedure is described which enables high power VCSELs to be made for high power operation at many different wavelengths. A low temperature electrical contacting process improves VCSEL long term reliability.

Described herein are methods for flattening a substrate, such as a semiconductor wafer, to reduce bowing in such substrates. Methods include treating or bombarding a backside surface of a substrate with particles of varying doses, densities, and spatial locations. Particle bombardment and selection is such that the substrate becomes more planar by selectively increasing or decreasing z-height points to reduce overall deflection. One or more tensile or compressive films can be added to the backside surface to be selectively relaxed at specific point locations. Such methods can correct bowing in substrates resulting from various fabrication processes such as thermal annealing.

Methods for adaptive real time control of a system for thermal processing substrates, such as semiconductor wafers and display panels. Generally, the method includes creating a dynamic model of the thermal processing system, incorporating wafer bow in the dynamic model, coupling a diffusion-amplification model into the dynamic thermal model, creating a multivariable controller, parameterizing the nominal setpoints, creating a process sensitivity matrix, creating intelligent setpoints using an efficient optimization method and process data, and establishing recipes that select appropriate models and setpoints during run-time.

Techniques herein include systems and methods for correcting pattern overlay errors by correcting or adjusting bowing of wafers. Location-specific tuning of stress on semiconductor substrates reduces overlay error. Location-specific tuning of stress independently modifies specific regions, areas, or point locations on a substrate to change wafer bow at those specific locations, which reduces overlay error on substrates, which in turn improves overlay of subsequent patterns created on the substrate. Techniques herein include receiving a substrate with some amount of overlay error, measuring bow of the substrate to map z-height deviations across the substrate, generating an overlay correction pattern, and then physically modifying internal stresses on the substrate at specific locations with modifications independent of other coordinate locations. Such modifications can include etching a backside surface of the substrate. One or more processing modules can be used for such processing.

Structures and methods for reducing wafer bow during heteroepitaxial growth are described. Micro-trenches may be formed across a surface of a substrate and filled with polycrystalline material. Stress-relieving regions of material can be grown over the polycrystalline material in a layer of semiconductor material during heteroepitaxy.

Easily removable heteroatom-doped carbon-containing layers are deposited. The carbon-containing layers may be used as hardmasks. The heteroatom-doped carbon-containing hardmasks have high etch selectivity and density and also a low compressive stress, which will reduce or eliminate problems with wafer bow. Heteroatoms incorporated into the hardmask include sulfur, phosphorous, nitrogen, oxygen, and fluorine, all of which have low reactivity towards commonly used etchants. When sulfur is used as the heteroatom, the hardmask is easily removed, which simplifies the fabrication of NAND devices, DRAM devices, and other devices.

The invention proposes a method and device for detecting wire bows during the cutting process of photovoltaic silicon wafers, which can effectively solve the problems of insufficient precision and inconvenient operation existing in the prior art. The device for detecting the wire bow is to fix a telescopic lens with a transparent scale outside the photovoltaic silicon wafer cutting work area, and there is a cross mark in the center of the lens; set the viewing angle of the telescopic lens to observe the wire bow as θ, and measure the distance from the telescopic lens to the cutting wire net The horizontal distance L0 to the junction point of the silicon rod and the height h0 relative to the cutting line network are calculated according to the corresponding relationship between θ and h embodied by h=L0tanθ‑h0 and the vertical height value is marked on the transparent scale, which is used for direct observation. The value h of the wire bow. The detection result of the present invention is accurate (the precision is 1mm); during the detection, it is not necessary to repeatedly open and close the cutting chamber during the cutting process; at the same time, continuous observation is realized, which greatly reduces the detection difficulty of technicians.

We describe a method for reducing bow in a composite wafer comprising a silicon wafer and a silicon carbide layer grown on the silicon wafer. The method includes applying nitrogen atoms during the growth process of the silicon carbide layer on the silicon wafer so as to generate a compressive stress within the composite wafer.

In some examples, a wafer bow measurement system comprises a measurement unit including: a wafer support assembly to impart rotational movement to a measured wafer supported in the measurement unit; an optical sensor; a calibration standard to calibrate the optical sensor; a linear stage actuator to impart linear direction of movement to the optical sensor; a wafer centering sensor to determine a centering of the measured wafer supported in the measurement unit; and a wafer alignment sensor to determine an alignment of the measured wafer supported in the measurement unit.